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I've just finished the first pass of layout on a board in Eagle, and I turned on all the board layers and ran a design rule check. I got a considerable number of errors, because a number of my parts that I'm using from Eagle's builtin libraries have tiny >VALUE labels right in their centers, under the stop mask. This yields stop mask DRC errors for every vector in the label. In the image below, I've used a stock TPPAD1-13 from the Eagle library testpad.

Test pad with tiny value

The offending value label can be seen in the very center of that test pad. I've found that I can smash the package, then set the value label's display attribute to off, which makes it disappear, but I'm not positive this is the best way, nor do I want to do this for every part – there are over 900 similar errors.

So, two questions:

  • Why were these packages designed this way?
  • What is the best way to fix the errors caused by these labels?
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Why were these packages designed this way?

I can't say for sure why you have the very tiny label on that particular part. Perhaps the idea was to make it "disappear" without deleting it altogether. This allows it to still appear on a BOM, for example.

In general, the value field is not normally used in the silkscreen at all, except maybe in certain educational projects or kits.

Normally, the value field is used only in an assembly drawing, where it just needs to be small enough to match the general size of the part on the drawing.

What is the best way to fix the errors caused by these labels?

As I said above, simply don't include the value field in your silkscreen layer. This is why "names" and "values" have their own layers in the design stack.

Otherwise, it would probably be worth your while to create a custom library that has the labels the way you want them.

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  • \$\begingroup\$ I see. If I don't include that value layer in the silkscreen output, that will make these errors irrelevant. Is there a way to change my DRC configuration to prevent it complaining about objects in the value layer, or must I simply approve all 900+ DRC errors resulting from this issue? \$\endgroup\$ – ravron Mar 1 '15 at 17:04
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    \$\begingroup\$ Turn off the value layer in your display before you run DRC. DRC only works on the layers that are currently visible. \$\endgroup\$ – Dave Tweed Mar 1 '15 at 17:19
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    \$\begingroup\$ @DaveTweed this is absolutely correct and one of the bigger things I find that "1 step up" from newbies run into. Newbies don't know about DRC, but the next level of enlightenment often doesn't know that you must have all the layers you want checked visible. This leads to boards being produced that "pass DRC" yet have shorts or other issues. \$\endgroup\$ – akohlsmith Mar 1 '15 at 17:25
  • \$\begingroup\$ Ah, ok. I had noticed this behavior, but I wasn't sure it was "proper" to use it in that manner. Thanks! \$\endgroup\$ – ravron Mar 1 '15 at 17:31
  • \$\begingroup\$ Note also that (at least in the CAD packages I've used) DRC errors will not prevent the program from producing Gerber and drill files. The program just considers the DRC error messages to be warnings to the operator. It is OK to have a few DRC errors on a finished board, provided that you know why the are there, and are satisifed that the board is really OK. Of course, it is best if there are no DRC errors, but sometimes they can't be avoided without excessive work on the design rules. \$\endgroup\$ – Peter Bennett Mar 1 '15 at 17:38

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