# Why do N-channel MOSFETs have a voltage drop when load is connected on source side?

I read how MOSFETs work, although there is this thing I can't understand. To make things simpler let's take only n-channel MOSFETs into account. Normally, the load is connected on the drain side, like this:

When $V_{GS}$ is above $V_{thres}$ and high enough for the desired current to conduct, the MOSFET is in full saturation, and the effective resistance is low, making the $V_{DS}$ very small. This happens even if $V_{DS}$ is higher or lower than $V_{GS}$.

However, if you connect the load on the source side, like this:

In order for the MOSFET to go into full saturation, it's required that $V_{GS} > V_{DS} + V_{thres}$. Why is that? The load is still in the same current path; does it somehow lower the effective voltage at the drain (in the first case) so that $V_{DS} < V_{GS}$ before current flows?

• It would be very helpful if you could add a schematic of each arrangement to your question. – Greg d'Eon Mar 2 '15 at 3:43
• Sorry it doesn't show all my message here is the rest: The load is still in the same current path, does it somehow lower the effective voltage going into drain (in the first case) so that the effective Vds<Vgs before current flows? I'm really confused why is this happening. I would really appreciate if someone explains me why this is happening. Thanks! – TnF Mar 2 '15 at 3:44
• You can press the edit button to change your original question - don't add extra details in the comments. – Greg d'Eon Mar 2 '15 at 3:45
• Here is a simulation i made. Load connected to drain: i.imgur.com/3fkWXbJ.png and source: i.imgur.com/pgB75al.png Please click to zoom image to full res. – TnF Mar 2 '15 at 3:45
• @Kynit Thanks for the edit, you are really good :) edit: maybe you can add links too for the images to load in a separate window so that other people don't think that are low resolution pics – TnF Mar 2 '15 at 4:00

The difference between the gate voltage and the channel voltage needs to be above the threshold voltage for the MOSFET to conduct well. If the load is between the mosfet and ground, then the more current you push through the mosfet, the more voltage drops over the load and the less gate-source voltage there is.

In the first topology, it doesn't matter how much voltage is dropping across the load, the mosfet always sees Vg - Vs, where Vs is always 0. In the second case, Vs rises with the load current and in turn pinches the mosfet back towards "off". So in the second case, you have Vg - Vs where Vs starts at 0 and increases according to I_load*R_load.

You're effectively lowering Vgs by putting the load below the Nmos.

• Thanks for the reply. This does make sense now. I have another question regarding the usage of a mosfet as a buffer amplifier. I think is better to make a new question. Thanks again and sorry i cannot vote up! – TnF Mar 2 '15 at 4:38
• @TnF Glad it helped. Though you can't vote yet, you can mark answers as "Answered" if you think a response is the answer you're after. – horta Mar 2 '15 at 14:36

The reason you are seeing the effect is as follows:

When you put the load between the source and GND then when the N-FET starts to turn on there is voltage drop across the load. This voltage drop is due to the current through the load and the resistance of the load. This voltage drop effectively pushes the source terminal above GND. Pushing the source terminal up like this makes any gate drive be a lower amount by the amount the source is pushed up.

If this effect is pronounced enough it can even tend to begin to take the N-FET out of saturation and start to push it into the linear range. This will result in a greater VDS drop as the channel resistance of the FET rises.