I'm attempting to use bit-slice design, to implement a circuit which checks if an n-bit binary number A has an even number of 1's in its binary representation. I've decided that the circuit should produce an output of 0 if the number of 1's is odd, or 1 otherwise.

I'm currently fixated on one scenerio where the bit slice communicates the sum of the previous bits, a(i-1), with the current bit, a(i), all by ignoring the carry bit. It will transmit this sum to the next bit slice. Essentially , if a N-bit binary number is even, the final output sum will be 0, in which case I would invert the last sum bit. I'm not totally convinced on my approach, is there a better approach?

This is my current truth table: s(i) works like a check bit in a full adder circuit. At least the way I modeled it. Honestly, I feel like I'm doing this wrong.

a(i)    s(i)     output

 0       0         1

 1       0         0

 0       1         1

 1       1         0
  • \$\begingroup\$ I don't think anything is wrong with your approach, except that it is slow (takes N delay staps for N bits). PS do you recognize the thruth table? \$\endgroup\$ – Wouter van Ooijen Mar 2 '15 at 6:39
  • \$\begingroup\$ what is s(i) ? \$\endgroup\$ – nidhin Mar 2 '15 at 10:49

You are calculating the one-bit parity of your n-bit input. The standard way to do this is with a tree of 2-input XOR gates, which minimises the gate count and depth.

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There is nothing wrong in your approach:

sum = 0
for i=1:n loop
   sum = sum + a(i)
output = !sum

But I don't see a need for full-adder here. You can implement this logic using half adder or XOR gate.

XOR will be a better alternative: output = !(a(1) xor a(2) xor ... xor a(n))


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