How did they get to the SR-latch with 2 NOR gates?

Question

I understand SR latches and how they work, but I was trying to recreate the SR latch to see if I can get to the same well known circuit with 2 NOR gates.

However if I write the following logic table for an SR-latch | S | R | Q | Q+ | | --- | --- | --- | --- | | 0 | 0 | 0 | 0 | | 0 | 0 | 1 | 1 | | 0 | 1 | 0 | 0 | | 0 | 1 | 1 | 0 | | 1 | 0 | 0 | 1 | | 1 | 0 | 1 | 1 | | 1 | 1 | 0 | x | | 1 | 1 | 1 | x |

and solve the K-map for this table, I get Q+ = S + Q!R and !Q+ = R + !Q!S. Even if I apply DeMorgan, I get Q+ = S + !(!Q + R) and !Q+ = R + !(Q + S) and the resulting circuit:

^{simulate this circuit – Schematic created using CircuitLab}

So how did they get to that simple form using only 2 NOR or NAND gates?

Answer 1

Generally, an RS latch will be used in situations where both inputs will never be active simultaneously, and thus the behavior of the circuit in such cases won't matter. The effect of the extra "or" gates is to make it so that when both inputs are true, both outputs will also be true; in their absence, having both inputs be true would force both outputs to be false. If one needs the outputs to both be true when both inputs are true, then the extra gates will be required. In cases where it would be acceptable for both outputs to be false as long as both inputs were true, however, the OR gates may be omitted (simply wire the outputs to the input that came from a NOR gate) since they do not affect behavior in other cases.

Answer 2

Your lines from S and R into their respective OR gates are redundant with the lines going into the opposite NOR gates.

i.e. S high will feed through the top OR gate (Q) which goes into one of the inputs to the bottom NOR gate. But S goes into this same NOR gate, and since it acts as an OR (as far as the inputs go), you don't need to have the S feeding the top OR gate input.

Take S away from the top OR gate, and you have the equivalent of a straight wire. Remove both of the OR gates and you have the standard SR latch made with NOR gates.

So your truth can be simplified. You have two entries for S=0 and R=1, and two for S=1 and R=0. But they both give the same result, so you can consolidate them into one and show an x for the current value of Q. It doesn't matter what Q is for either of these: if S=1 and R=0; Q+ will be 1 regardless of Q. Similarly, if S=0 and R=1, Q+ will be 0 regardless of Q.

So Q+ = S, and !Q+ = R.

 | S | R | Q | Q |
 |---|---|---|---|
 | 0 | 0 | 0 | 0 | 
 | 0 | 0 | 1 | 1 |
 | 0 | 1 | x | 0 |
 | 1 | 0 | x | 1 |
 | 1 | 1 | 0 | 0 |
 | 1 | 1 | 1 | 1 |