I understand SR latches and how they work, but I was trying to recreate the SR latch to see if I can get to the same well known circuit with 2 NOR gates.
However if I write the following logic table for an SR-latch
| S | R | Q | Q+ |
| --- | --- | --- | --- |
| 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 1 |
| 0 | 1 | 0 | 0 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 0 | 1 |
| 1 | 0 | 1 | 1 |
| 1 | 1 | 0 | x |
| 1 | 1 | 1 | x |
and solve the K-map for this table, I get Q+ = S + Q!R and !Q+ = R + !Q!S. Even if I apply DeMorgan, I get Q+ = S + !(!Q + R) and !Q+ = R + !(Q + S) and the resulting circuit:
simulate this circuit – Schematic created using CircuitLab
So how did they get to that simple form using only 2 NOR or NAND gates?