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As an engineering student, I'm trying to think of an analog equivalent to a flip-flop. My goal is to have a short term memory of a signal, saturating the transistor being the trigger. Kind of like an analog D flip flop.

A simplified version of the circuit

Here is how I hope this would work :

  • When Q1 is saturated, C1 quickly takes the same voltage as the input (like an RC circuit, with R close to 0).
  • When Q1 is left alone, C1 keeps its charge, since the input of an OP amp is supposed to behave like an infinite resistor. Since the OP amp is in a following montage, the output voltage should be the same as C1's.

So I believe this could work, but can't experiment on it. Of course I know the OP amp isn't perfect, but my hope is that it could still be good enough to preserve C1's charge for a few milliseconds.

What do you think ? Is there some obvious mistake in there that I didn't account for ? Or could this actually work ? I lack the materials to build and try this system myself for now but I'm curious. My goal would be to put it in front of an ADC in order to presample my input.

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    \$\begingroup\$ Why don't you just buy a sample and hold amp or maybe an ADC with one built in. There are plenty to choose from. \$\endgroup\$ – Andy aka Mar 3 '15 at 17:24
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What you are building is a sample and hold circuit. It's at the front-end of many (most?) ADCs.

Sample and hold - WikiPedia article

To make it a "memory" you basically have to balance your refresh of the value in the capacitor vs. the size of the capacitor.

Dynamic random-access memory - WikiPedia article

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The basic topology is sound.

You can use a CMOS analog switch rather than a BJT. There is a trade-off between the acquisition time and how fast the voltage changes due to leakage. Most of the leakage will likely be from the switch rather than the op-amp if you choose a very good op-amp.

If you used a glass-encapsulated reed switch, a very high quality capacitor and an electrometer grade op-amp you could get extremely low leakage current- in the pA or even fA.

Using less exotic and inconvenient components, a few tens of nA leakage (typical) is quite achievable so if the cap is 1uF, you'd get a drift of 50mV/second with 50nA leakage/bias current. So, in 5ms, the voltage would change 250uV. If the switch + source has a resistance of 100 ohms, it would take (say for 5 time constants) 0.5msec to acquire the voltage (could be sped up by tricks).

You'll also get some inaccuracy effects due to charge injection of the switch (a transient and a step change when the switch switches) and due to dielectric absorption of the capacitor.

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    \$\begingroup\$ This would appear to be the best answer yet, but I'm not sure about "the basic topology is sound". OP's circuit allows the capacitor to be charged, but (as far as I can see) not discharged. So if the sampled voltage is lower than the previous one, the circuit will fail. I'd suggest an op-amp buffer, then a CMOS switch, then the capacitor based circuit. \$\endgroup\$ – abligh Mar 3 '15 at 19:48
  • \$\begingroup\$ @abligh In the topology, the BJT represents a controlled switch (that's what he means by saturate). As far as the specific circuit goes, with a bipolar drive on the transistor base it will actually work as drawn up to about the base current (will drive the cap in both directions). The drive voltage compliance must exceed the signal voltages and be current limited. Of course the source impedance is assumed to be negligible, otherwise a buffer should be used. \$\endgroup\$ – Spehro Pefhany Mar 3 '15 at 21:14
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What you shown in the question is the sample-and-hold circuit. It will work as the short term analog memory as you said in the question. Actually it is intended to work that way.

Most of them use a MOSFET instead of BJT.

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If you want to design an addressable analog memory, using an op amp per bit probably isn't the best way to go about it. The amount of circuitry per bit may be reduced to a capacitor, a diode, an NPN transistor, and a digital logic gate that can drive clean CMOS levels.

schematic

simulate this circuit – Schematic created using CircuitLab The three horizontal wires above should connect all the memory cells. Each cell must be erased before writing.

When idle, the diode anode should be at ground, and the common collector and emitter at twice VDD.

To erase some memory cells, have the digital outputs feeding all the memory cells output low, float the common collector, and clamp the common emitter to VDD-0.7V, and have digital outputs feeding the memory cells to be erased output high.

To store a voltage, float the common emitter, have all digital outputs that should be left alone output high and the one to be written output low. Then put the desired voltage plus 0.7V on the common diode anode.

To read a voltage, drive the common collector with 2x VDD, drive low on all the digital outputs, weakly pull down the common emitter, and drive the output for the cell of interest high. The common collector voltage will then be be VDD above the stored voltage (though some charge will leak out slowly through the transistor base).

Note that because the "unique" wire on each capacitor is tied to a digital output, it would be possible to use a "grid" of analog voltage cells, with each digital output connected to multiple memory cells. I'm not sure that would be particularly worthwhile for any reasonable number of cells, however.

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