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When sharing a crystal oscillator output to multiple clock inputs, what should the oscillator output PCB tracks topology be ? Should they go from the oscillator output to one clock input to the next clock input and so on (chaining) ? Should they all start at the oscillator output and connect independently to the clock inputs (star) ? Is it unimportant ?
Thank you !
It is quite important how you design the clock traces. It will also depend on the clock frequency. Remember, clock traces running at higher frequency than 1 MHz(approximated), your traces are no longer lumped. They are now transmission lines. Most likely you would want to design your trace line to be 50 ohm line (easy to make with adjusting pcb dielectric and trace parameters). You would have to make sure to match your transmission line with 50 ohm at all receivers to avoid. Untreminated lines will cause glitches/reflections in your clock at receiver which you dont want to see at receiver. There are many standard clock interface topologies for transmission line which are usually given by the clock receiver or clock fanout buffer manufacturers. I have posted some links below which are very useful. Some receivers already have internal termination but some might not. If they don't, you would have to add external termination resistors. Again, how and where you connect termination resistor and which termination resistor values to be used are given by following links. Another tip might be to use ADS or pspice simulations using IBIS models that are usually provided by the clock buffers and receivers.
http://www.ctscorp.com/components/appnotes/AN1025_ClockTerminationDesignGuidelines.pdf
http://www.cn-william.com/e2v/ad-ap/Input-Output%20Termination%20Techniques.pdf
http://www.physics.ohio-state.edu/~hughes/cdf_osu/xft/documents/layout.pdf
