When sharing a crystal oscillator output to multiple clock inputs, what should the oscillator output PCB tracks topology be ? Should they go from the oscillator output to one clock input to the next clock input and so on (chaining) ? Should they all start at the oscillator output and connect independently to the clock inputs (star) ? Is it unimportant ?

Thank you !

  • 1
    \$\begingroup\$ How long are the traces on your PCB and what frequency are you typing about? \$\endgroup\$
    – jippie
    Commented Mar 4, 2015 at 19:27
  • \$\begingroup\$ There is a rule. Oscillator should be very, very close to the IC. Especially in high frequency circuits. \$\endgroup\$ Commented Mar 4, 2015 at 19:29
  • \$\begingroup\$ 25Mhz, under 8mm total from output to both inputs (in star topology) or under 12mm total from output to input #1 to input #2 (chaining). \$\endgroup\$
    – Koen
    Commented Mar 4, 2015 at 19:30
  • 2
    \$\begingroup\$ 8mm total for 25Mhz? No worries. \$\endgroup\$
    – Tut
    Commented Mar 4, 2015 at 19:37
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    \$\begingroup\$ High-Speed Layout Guidelines from TI may be of interest. Particularly the section on "Clock Distribution", although as I said, for that short distance you really have no worries as the distance is very much less than a wavelength or even reflections relative to fast rise times. \$\endgroup\$
    – Tut
    Commented Mar 4, 2015 at 20:14

1 Answer 1


It is quite important how you design the clock traces. It will also depend on the clock frequency. Remember, clock traces running at higher frequency than 1 MHz(approximated), your traces are no longer lumped. They are now transmission lines. Most likely you would want to design your trace line to be 50 ohm line (easy to make with adjusting pcb dielectric and trace parameters). You would have to make sure to match your transmission line with 50 ohm at all receivers to avoid. Untreminated lines will cause glitches/reflections in your clock at receiver which you dont want to see at receiver. There are many standard clock interface topologies for transmission line which are usually given by the clock receiver or clock fanout buffer manufacturers. I have posted some links below which are very useful. Some receivers already have internal termination but some might not. If they don't, you would have to add external termination resistors. Again, how and where you connect termination resistor and which termination resistor values to be used are given by following links. Another tip might be to use ADS or pspice simulations using IBIS models that are usually provided by the clock buffers and receivers.





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