I am solving problems on DC analysis of MOSFET circuits. We are supposed to find various parameters like Id(Drain Current) and voltages at various nodes like Vg(Gate Voltage).
The MOSFETS used are both NMOS(n-channel enhancement type)
In my book, where circuits of first type are concerned, Vg is given by
Vg=[R3/(R2+R3)]*Vdd ____________ eqn 1 (I figure this is because resistors R3 and R2 form a voltage divider network. Correct me if i am wrong)
However for circuits of second type, Vg is calculated by
Vg=[R3/(R2+R3)]*(Vdd-(-Vdd)) - Vdd _______________ eqn 2
I don't understand why Vdd is being subtracted. I scanned all the pages of my book looking for a one-line explanation but didn't get any. I also tried joining the 2 nodes to form a third loop and then use KVL(Kirchoff's Voltage Law) but I just don't get it.
Can someone explain me the equations 1 and 2?
PS: This is my first question on this site so general tips about asking specific,easy to read questions and courting quick answers will be appreciated. Have a good day.