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It is a known fact that over time processors (or chips) are becoming smaller and smaller. Intel and AMD are in a race for the smallest standards (45nm, 32nm, 18nm, ..). But why is it so important to have the smallest elements on the smallest chip area?

Why not make a 90nm 5x5cm cpu? Why squeeze 6 cores into a 216mm2 area? It will be easier to dissipate the heat from larger area, manufacturing will require less precise (and thus cheaper) technology.

I can think of few reasons:

  • less size means more chips could be made on single wafer (but wafers aren't very expensive, right?)
  • smaller sizes are important for mobile gadgets (but everyday PCs still use tower boxes)
  • small size is dictated by light-speed limit, the chip can't be larger than the distance an EM field can travel in 1 cycle (but thats approximately several cm at 3GHz)

So, why do chips need to become smaller and smaller?

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    \$\begingroup\$ more is law? :) \$\endgroup\$ – kenny Jun 23 '11 at 12:41
  • \$\begingroup\$ in the majority of cases the final package size, what matters for fitting it in a cell phone, is determined by the type of packaging and pin count. In other words the actual die size is generally much smaller than the package would indicate, even for larger processes. Packaging is a large portion of the cost of manufacturing a high pin count IC, much more than you would think and sometimes more than manufacturing the actual die. \$\endgroup\$ – Mark Jun 23 '11 at 22:24
  • \$\begingroup\$ @Mark - Cell phone manufacturers want more and more CSP (Chip Scale Packages), which are almost the same size as the die. You can hardly justify packages like TQFP in smartphones anymore, they're too space-inefficient. \$\endgroup\$ – stevenvh Jun 25 '11 at 16:15
  • \$\begingroup\$ @stevenvh I think we said the same thing, packaging choices and condensing of multiple chips into one package to reduce pin count and external component needs are primarily driving the miniaturization of ICs for cell phone use. Process size is generally not the limiting factor, especially in high pin count devices. \$\endgroup\$ – Mark Jun 25 '11 at 16:39
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    \$\begingroup\$ To be clear, the CPUs are not actually becoming smaller. They are remaining roughly the same size but containing more and more transistors because the size of each transistor is decreasing. \$\endgroup\$ – David Schwartz Aug 21 '11 at 6:34
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It's like candy bars. They keep making them smaller at the same price to increase profit.

Seriosly though, there are good reasons for smaller chips. The first and foremost is that more chips can be fit onto a wafer. For large chips, the cost is all about what fraction of a wafer it uses. The cost to process a wafer is pretty much fixed, regardless of how many chips result from it.

Using less of the expensive wafer is only one part though. Yield is the other. All wafers have imperfections. Think of them as being small but randomly scattered about the wafer, and any IC that hits one of these imperfections is trash. When the wafer is covered by lots of small ICs, only a small fraction of the total are trash. As the IC size goes up the fraction of them that hit a imperfection goes up. As a unreal example that nonetheless points out the issue, consider the case where every wafer has one imperfection and is covered by one IC. The yield would be 0. If it were covered by 100 ICs, the yield would be 99%.

There's a lot more to yield than this, and this is greatly oversimplifying the issue, but these two effects do push towards smaller chips being more economical.

For really simple ICs, the packaging and testing cost dominates. In those cases, the features size is not so much a driving issue. This is also one reason we have seen a explosion of smaller and cheaper packages lately. Note that extreme small features size is being pushed by very large ICs, like main processors and GPUs.

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    \$\begingroup\$ Also the silicon ingot is round so you lose more chips per wafer as the chips get bigger, ie. you can fit more smaller square chips into a circle. \$\endgroup\$ – Martin Jun 23 '11 at 12:24
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    \$\begingroup\$ +1 @Martin, not to mention it's at the edges of the wafer we many device failures are found. \$\endgroup\$ – kenny Jun 23 '11 at 12:44
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    \$\begingroup\$ @endolith: Think of how zone refinement works. A circular crossection is the optimum shape for that. \$\endgroup\$ – Olin Lathrop Jun 23 '11 at 18:44
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    \$\begingroup\$ The holes around the edge can be filled with smaller dice if and only if the structure (substrate doping, transistor technologies, metalization layer count, etc.) is the same for both the larger and smaller dice. Additionally, production rates for the two devices become linked and may not be similar to the demand rate for the two different parts. Therefore, it is rare when you can get away with that trick. \$\endgroup\$ – Mike DeSimone Aug 21 '11 at 16:10
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    \$\begingroup\$ The wafer has to be round because of the manufacturing process. To create a single crystal of silicon, a starter crystal is dipped into a bath of molten, doped silicon, and slowly withdrawn while rotating the crystal. Precise control of rotation and extraction speed determines both the diameter of the crystal and prevents formation of polycrystalline defects. The diameter and length are also limited by mechanical considerations, i.e. how much you can pull before it breaks off and falls back in. After this, it is cut into wafers and polished. \$\endgroup\$ – Mike DeSimone Aug 21 '11 at 16:14
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As the process size gets smaller, power usage decreases.

Smaller transistor processes allow the use of lower voltages combined with the improvements in construction technique mean that a ~45nm processor can use less than half the power that a 90nm processor uses with similar transistor counts.

The reason for this is that as the transistor gate gets smaller, threshold voltage and gate capacitance (required drive current) gets lower.

It should be noted that as Olin pointed out this level of improvement doesn't continue to smaller process sizes as leakage current becomes very important.

One of your other points, the speed at which signals can travel around the chip:

At 3ghz the wavelength is 10cm, however the 1/10th wavelength is 1cm which is where you need to start considering transmission line effects for digital signals. Additionally remember that in the case of Intel processors some parts of the chip runs at twice the clock speed so 0.5cm becomes the important distance for transmission line effects. NOTE: they may be operating on both clock edges in this case, meaning the clock doesn't run at 6Ghz but some processes going on are moving data that fast and have to consider the effects.

Outside transmission line effects, you also have to consider clock synchronization. I don't actually know what the propagation velocity is inside a microprocessor, for unshielded copper wire its like 95% of the speed of light but for coax is like 60% the speed of light.

At 6Ghz the clock period is only 167 picoseconds the so high/low time is ~ 84 picoseconds. In vacuum, light can travel 1cm in 33.3 picosends. If the propagation velocity was 50% the speed of light then its more like 66.6 picoseconds to travel 1 cm. This combined with the propagation delays of the transistors and possibly other components means that the time the signal takes to move around even a small die at 3-6Ghz is significant for maintaining proper clock synchronization.

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    \$\begingroup\$ Power goes down with feature size to a point. The lower switching voltages make the ratio of the FETs on and off state smaller. This means there is considerable off state leakage to get low enough on state impedance. As a result, leakage power is a significant fraction of the power required to run some modern processors. Power still goes up with clock rate, but the maximum clock rate is limited by the subtantial leakage power always present. There are lots of interesting tradeoffs in modern processors, and the ballances between them change rapidly. \$\endgroup\$ – Olin Lathrop Jun 23 '11 at 14:45
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    \$\begingroup\$ Your light is ten times too fast: 3.33×10^-12 s × 3×10^8 m/s = 10^-3 m = 1mm. \$\endgroup\$ – starblue Jun 23 '11 at 16:20
  • \$\begingroup\$ @Olin Lathrop Agreed, in the most recent generations leakage is the major limiter. I was mostly referencing the transition from 90nm to 45nm which does have a nearly linear decrease in power. That linearity isn't there under 45nm as you've said. \$\endgroup\$ – Mark Jun 23 '11 at 22:07
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The main reason is the first one you mentioned. Wafers (what you call plates) are very expensive, so you want to get the most from them. Earlier wafers were 3 inch in diameter, today's are 12 inch, which not only gives you 16 times as much real estate, obviously, but you get even more dies out of them than that.
So it's clear that they would use this technology also for CPUs used in tower PCs, even if it doesn't look like it's necessary there. And don't forget that laptop PCs also have this kind of CPUs, and they are on a budget as far as space is concerned.
Speed is also a concern, at 3 GHz signals travel less than 10 cm per clock cycle. As a rule of thumb from 1/10th of that we have to take care of transmission line effects. And that's less than 1 cm.

edit
Smaller feature size also means less gate capacitance, and this allows for higher speed. Faster switching means less power consumption, since MOSFETs will go faster through their active region. In practice manufacturers take advantage of this to clock faster, so that in the end you won't see much of this power reduction.

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    \$\begingroup\$ 300 000 000 meters / 3 000 000 000 Hz = 0.1 meter, thats 10cm, right? \$\endgroup\$ – Kromster Jun 23 '11 at 12:34
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    \$\begingroup\$ Wafers are cheap, 100$ per wafer. What is expensive is explosure - steppers can process 120 wafers per hour max, and each wafer need up to 20 explosures. \$\endgroup\$ – BarsMonster Jun 23 '11 at 12:39
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    \$\begingroup\$ @BarsMonster can't explosure ruin a wafer? Sorry! :) \$\endgroup\$ – kenny Jun 23 '11 at 12:43
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    \$\begingroup\$ @kenny Physical damage to wafer is highly unlikely at modern fab. Microscopic defects - they are always here. \$\endgroup\$ – BarsMonster Jun 23 '11 at 12:54
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    \$\begingroup\$ @stevenvh: yes, what BarsMonster said. When have a million-dollar sputtering machine, and it processes a hundred thousand (?) wafers over its lifetime, it's simplest to think of it and the other machines at the fab as part of the "total cost per wafer". The fraction of the "total cost per wafer" that comes from buying the unmasked pure silicon disks is almost insignificant. \$\endgroup\$ – davidcary Jul 23 '11 at 16:19
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The CORE reason why CPUs keep getting smaller is simply that, in computing, smaller is more powerful:

To a first approximation, computation involves two basic actions: transmitting information from one place to another, and combining strands of information to produce new information. Since we are used to using electronics here, let's call the hardware for these actions 'wires' and 'switches'. For both of these, smaller is better:

Wires: Since the speed of transmission on a wire is essentially constant, then if you want to get information from one place (e.g switch) to another, you have to shorten the wire. (you may be able to achieve a faster speed, but eventually you hit the speed of light limit, at which point you are forced back to shortening).

Switches: A switch works by information from one or more input wires entering and suffusing the body of the switch, causing its internal state to transform so as to modulate the information on one or more output wires. It simply takes less time to suffuse the body of a smaller switch.

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