I am working with the STM32F4 microcontrollers. The I2C peripheral uses a clock setting.
I have been told that it does not matter when the peripheral is used as the slave device.
If that is true how is the proper hold time, alignment, and spacing before and after master clock edges maintained? i.e. If the clock falling edge of the master is received, and the slave device assumes a very slow clock rate, isn't it possible the slave device will change the data line too late, possibly after the next clock rising edge is received?