Slave I2C timing relative to master clock edges

Question

I am working with the STM32F4 microcontrollers. The I2C peripheral uses a clock setting.

I have been told that it does not matter when the peripheral is used as the slave device.

If that is true how is the proper hold time, alignment, and spacing before and after master clock edges maintained? i.e. If the clock falling edge of the master is received, and the slave device assumes a very slow clock rate, isn't it possible the slave device will change the data line too late, possibly after the next clock rising edge is received?

Answer 1

The bus master provides the clock. Therefore, the slave doesn't need to have clock generation parameters, as it's not generating the clock.

The slave doesn't need to know the speed of the clock coming in. It receives the falling edge of the clock, and then changes the data as soon as it can. In fact, it's required (by the spec) to change it within a certain time period of the falling edge of the clock (e.g. within 3.45 us in standard (100 kHz) mode).

The master will then latch the data on the rising edge of the clock. This cannot come "too soon" for the changed data to have arrived, because the spec again requires that the master's clock can't be too fast (min. low period of 4.7 us in standard mode).

There are other complications around hold times and limiting slew rates depending on which version of the I2C spec you're dealing with (and therefore which data rate you're using), but I won't go into that.