I have a design where power savings is a huge issue and even the lowest power sleep mode of the \$\mu\$C is too much quiescent current (30 \$\mu\$A). I'm aware of many and have used \$\mu\$Cs in the past that are extremely low sleep current (in the nA range), but I don't have the luxury of moving to a different \$\mu\$C in my current design (I promise this is the case due to constraints imposed upon me by the design team, otherwise I would migrate to a more optimal). Basically, we're as good as we can get for the \$\mu\$C we have to use and it's not good enough. So I'm not looking for new \$\mu\$C recommendations. I need a way to eliminate the sleep current of the \$\mu\$C or at least bring it down into the nA range.
One thought I had was remove power from the \$\mu\$C completely. That solves the quiescent current problem, but my fear is the unknown resistance of the \$\mu\$C when it is off. As datasheets don't normally list this figure, I think it would be safer to just isolate any digital I/O connected to the \$\mu\$C so they don't back-feed the \$\mu\$C (causing possibly even more current draw than the sleep mode did). Are there any good, ultra low-power schemes for this? I need to be in the nA range for quiescent current.
The design has a CPLD that is always on. With some clever clocking & manufacturer optimizations my CPLD should end up in the low \$\mu\$A range as well. I'm aware of this and have accepted this hit in power consumption due to design constraints. Could I route signals through that & employ some tri-state methods inside of the CPLD if needed?
The digital I/O I have connected are:
- Logic/interrupt lines