I'm getting conflicting info on whether I can use level-triggered (as opposed to edge-triggered) interrupts with the STM32F1xx microcontroller.
In ST's CMSIS-compliant Standard Peripheral Libraries, the trigger options
are defined in
enum EXTITrigger_TypeDef, which only includes
EXTI_Trigger_Rising_Falling. (no mention of level-triggered interrupts)
Also, ST's RM0008 Reference Manual doesn't make mention of level-triggered interrupts.
On the other hand:
ST's PM0056 Programming Manual, Section 4.3, states that:
The NVIC supports (...) Level and pulse detection of interrupt signals
The same document, Section 4.3.9, gives more detail about level-triggered and edge-triggered interrupts.
And the official ARM documentation, Section 4.2.9 says:
A Cortex-M3 device can support both level-sensitive and pulse interrupts. Pulse interrupts are also described as edge-triggered interrupts. (...) A level-sensitive interrupt is held asserted until the peripheral deasserts the interrupt signal.
However, I cannot find any way to actually set this up. I don't mind bypassing the Standard Peripheral Libraries, but I don't even see any appropriate registers to use...
I'm my specific case, I'm interfacing to another IC via SPI. It is a complex SOC, and it drives an output pin to signal that it needs attention. It communicates with it's "driver", which is hosted on the STM32. The SOC and driver want edge-triggering.
How can I configure the STM32F1xx to use level-triggered interrupts?