I am generating a 5V PWM signal from my MCU (an Atmel ATMEGA1284P). I need to convert this to a 12V PWM signal. For this I designed the circuit below, something very similar to a Sziklai pair, but adapted to match this case. It uses a bipolar NPN transistor to drive a bipolar PNP transistor. Ideally, I would need V_LOAD to be a 12.0 V PWM.
I ran a few simulations and this seemed to fulfill the purpose really well, until I remembered C_LOAD. Since V_LOAD is not actively pulled down when CLK2 goes low, the fall time is very long (too long, about 25 μs).
Any ideas on how to improve my design? Or should I trash this and use something else?
I apologize in advance if this has been asked before.
Some clarifications: The maximal current I'm going to drive will be around 10 mA. I have some pretty harsh specifications to fulfill: V_LOAD should be 12.0V and the rise and fall times (10%-90% = 1.2V-10.8V) should maximally be 2 μs,
EDIT: Thanks for your answers. Here's what I ended up using: Simulation.
It's based on Majenko's answer with two transistors added as gate drivers to reduce the time it takes for the PWM to go LO. Furthermore, MOSFET's with low gate capacitance have been chosen (BSS84P and BSS138). The fall time then becomes 3 μs.