I'm interfacing an SDI video de-serializer with an HDMI transmitter. The de-serializer splits the video signal into 20 parallel lines and one clock line.
Because the digital video data is high speed (in the 100's of MHz), I'm working on matching the lengths of each of the 21 traces (20 data + 1 clock). Unfortunately, the clock pins are located on opposite sides of both chips, so I have no choice but to cross the clock trace under all of the data lines or route the clock around all of the data traces. In the image below, the blue clock trace is crossing beneath the 20 red data traces.
I'm new to high-speed layout considerations, but I know that routing the clock signal next to any of the data traces is a bad idea due to cross-talk. However, this will be a 4-layer board, so there will be a ground plane between the top layer and bottom layer. With the presence of the ground plane between the clock and data lines, is it acceptable to route the clock crossing underneath the data traces as shown in the image? Or is it best to route the clock around everything else?
Note: The traces have not be length-matched yet in this image.