I'm interfacing an SDI video de-serializer with an HDMI transmitter. The de-serializer splits the video signal into 20 parallel lines and one clock line.

Because the digital video data is high speed (in the 100's of MHz), I'm working on matching the lengths of each of the 21 traces (20 data + 1 clock). Unfortunately, the clock pins are located on opposite sides of both chips, so I have no choice but to cross the clock trace under all of the data lines or route the clock around all of the data traces. In the image below, the blue clock trace is crossing beneath the 20 red data traces.

I'm new to high-speed layout considerations, but I know that routing the clock signal next to any of the data traces is a bad idea due to cross-talk. However, this will be a 4-layer board, so there will be a ground plane between the top layer and bottom layer. With the presence of the ground plane between the clock and data lines, is it acceptable to route the clock crossing underneath the data traces as shown in the image? Or is it best to route the clock around everything else?

enter image description here

Note: The traces have not be length-matched yet in this image.

  • \$\begingroup\$ The two middle traces that curve around and enter the pads from the inside are kind of odd. You should be fine to enter the pad from the side, why not do that? \$\endgroup\$ – Connor Wolf Mar 10 '15 at 4:36
  • \$\begingroup\$ @ConnorWolf, just a leftover artifact from an earlier iteration when the chips were closer together. Couldn't fit all 20 traces between the chips, so I was looking for ways to save space. When I start adding meander "wiggles" to length-match, I'll get rid of those. \$\endgroup\$ – Dan Laks Mar 10 '15 at 4:47

If they are using two different reference planes they should not interfere with each other. If they are on opposite sides of the same ref plane same thing they should not interfere. What does your Stackup look like?

  • \$\begingroup\$ it'll be top/ground plane/power plane/bottom. \$\endgroup\$ – Dan Laks Mar 10 '15 at 4:48

On a 4-layer board you shouldn't have an issue with crosstalk.

The one thing to thing about though is, as well as length matching you need to consider impedance matching - the characteristic impedance of the traces will need to match the requirements of the spec. I would suggest that you add a region of ground in your power plane layer underneath where the clock trace routes (extending out a bit either side of the trace so it appears as an unbroken plane) so that everything is matched to the same plane, this is just from what I have been told though, others may disagree.

Vias are a pain though because they can cause impedance mismatch issues unless correctly designed - so dropping the clock through the board and back again could cause issues if you don't design the vias correctly - it depends on frequency as to how badly it will affect it.

What I would suggest is to not drop down under the chip though - it makes designing a via harder as you become very space restricted. Instead I would bring it out as you have done the other lines, and then drop down. Cross under the data lines then pop back up. That way you can make the vias whatever size they need to be.

Alternatively having looked at it again, depending on what the other pins on the BGA are, you may be able to run the clock trace out through the corner of the QFN (left corner on your picture), then it should be able to get between the Data lines and you weave between the pins of the BGA to get to the clock pin - so no need to go on to the other side of the board.

But that depends on what the pins of the BGA do as the clock will have to route between them. Specifically what the function of D8, D9, D10, Q9, and Q10 is. If they are all ground for example it won't be an issue as you could get them all routed out. If they are unused, again not an issue.

Another option would be to route the clock around underneath the QFN and out the top corner, then it is on the correct side. If the QFN pad is ground you may get away with doing this as the coupling between the clock trace and the data lines over the short distance that each line will pass the clock should be negligible. Wouldn't be my first choice, but may be an option.


That clock is not really all that fast as the video bus is parallel at that point. You are probably looking at <220MHz or so assuming that is the usual AD7511.

My first instinct is to see if I could not put it on a more convenient ball on the FPGA, the ability to do that is after all the great virtue of the things.

Failing that do the via thing, but place a couple of 0402 decoupling caps right next to each via to provide a return path, and then play with the drive strength to get the jitter within spec.


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