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I came across this, which I'm guessing is correct, but I do not understand the shortcuts made here. What are the 8's with slashes through them? Do those represent 8 inputs and 8 outputs? And can someone explain the bottom part - the D(7:0) and D(15:8)? Assuming this is correct, that is.

1K X 16 ROM chip

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  • \$\begingroup\$ Yes, the number 8 next to a slash crossing a bus line indicates that it is an 8-bit bus, carrying either addresses or data. \$\endgroup\$ – Dave Tweed Mar 11 '15 at 18:12
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"What are the 8's with slashes through them?"

It shows that the interconnect is a 8-bit wide bus.

"And can someone explain the bottom part - the D(7:0) and D(15:8)?"

What the figure shows is 1K \$\times\$ 16 ROM. The data width is 16 bits. D(7:0) is the lower 8-bits of the 16-bit data line and D(15:8) is the higher 8-bit. So if you read the value at a particular address, the lower byte will be available at D(7:0) and higher byte at D(15:8).

"Assuming this is correct .."

Yes the answer given in the figure looks perfect to me.

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  • \$\begingroup\$ Okay. There are 8 outputs for each ROM though, and it seems that four ROMs with 8 outputs each go to the lower 8-bits of the 16-bit data line. How does that work? It seems to me 32 outputs are converted to 8 outputs. Forgive my ignorance. I am learning. And thank you. \$\endgroup\$ – Peter Griffin Mar 11 '15 at 19:11
  • \$\begingroup\$ "It seems to me 32 outputs are converted to 8 outputs." Exactly. At any given address, only one ROM is selected, so only that ROM's outputs are driving the bus. The other 3 ROMs are not selected, so their outputs don't affect the outputs. \$\endgroup\$ – WhatRoughBeast Mar 11 '15 at 23:33
  • \$\begingroup\$ Gotcha. Crystal clear. Those shortcuts in drawing the circuit threw me off. Thank you for taking the time to clarify things. \$\endgroup\$ – Peter Griffin Mar 12 '15 at 1:26

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