My question is if there is a way to reduce a clock to two thirds of its speed using flip flops because i know a flip flop cuts its speed in half.
Assuming your input clock is reasonably symmetric, you can use both edges of it, like this:
As long as the input duty cycle is close to 50%, the output will have two pulses for every three input pulses. The top part is a simple divide-by-three with a 1/3 duty cycle, and the extra FF on the bottom creates a second set of output pulses that happen midway between the first set. They get combined together by the final NOR (or OR) gate.
If the clock is fairly constant you can easily double it using an XOR gate. Feed clock to one pin and a delayed version of clock to the other.
The delay can be as simple as an RC low pass filter. This can be tailored to produce 2x clk frequency.
Next, implement a divide by three stage using flip flops and logic.
This is slightly simpler, if you're willing to accept the XOR gate.
Note that it requires the input clock to have a 50% duty cycle if you want the output to also have a 50% duty cycle. If the input is not symmetrical, the output will still have the proper 2/3 ratio, but the two phases will not be of equal duration.
ETA - Carp. Dave Tweed is correct. It produces divide by 3, not divide by 3/2. Actually, that was my first thought, but I went and convinced myself that I was wrong when I though I was mistaken.
In general, using fixed logic, you can't produce a symmetrical clock at the frequencies you want. The problem is that, for a frequency F, clock edges only occur at a 1/(2F) rate, and there's no way to tease out a factor of 3. If you are willing to produce a delay equal to 1/4 the period of the final frequency then you can take my circuit and add
If you're using CMOS, the delay can be a simple RC.