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My question is if there is a way to reduce a clock to two thirds of its speed using flip flops because i know a flip flop cuts its speed in half.

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  • \$\begingroup\$ So, you want to know if it's possible to, say, derive a 2MHz signal from a 3MHz clock if you only have flip-flops to do the work? \$\endgroup\$ – EM Fields Mar 11 '15 at 22:34
  • \$\begingroup\$ Actually both latches and flip flops as well as logic gates. \$\endgroup\$ – Μάριος Τσοκανάς Mar 11 '15 at 22:46
  • \$\begingroup\$ Are you doing this with discrete components, or inside an FPGA or similar device? \$\endgroup\$ – Aaron D. Marasco Mar 12 '15 at 0:20
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Assuming your input clock is reasonably symmetric, you can use both edges of it, like this:

schematic

simulate this circuit – Schematic created using CircuitLab

As long as the input duty cycle is close to 50%, the output will have two pulses for every three input pulses. The top part is a simple divide-by-three with a 1/3 duty cycle, and the extra FF on the bottom creates a second set of output pulses that happen midway between the first set. They get combined together by the final NOR (or OR) gate.

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If the clock is fairly constant you can easily double it using an XOR gate. Feed clock to one pin and a delayed version of clock to the other.

The delay can be as simple as an RC low pass filter. This can be tailored to produce 2x clk frequency.

Next, implement a divide by three stage using flip flops and logic.

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This is slightly simpler, if you're willing to accept the XOR gate.

schematic

simulate this circuit – Schematic created using CircuitLab

Note that it requires the input clock to have a 50% duty cycle if you want the output to also have a 50% duty cycle. If the input is not symmetrical, the output will still have the proper 2/3 ratio, but the two phases will not be of equal duration.

ETA - Carp. Dave Tweed is correct. It produces divide by 3, not divide by 3/2. Actually, that was my first thought, but I went and convinced myself that I was wrong when I though I was mistaken.

In general, using fixed logic, you can't produce a symmetrical clock at the frequencies you want. The problem is that, for a frequency F, clock edges only occur at a 1/(2F) rate, and there's no way to tease out a factor of 3. If you are willing to produce a delay equal to 1/4 the period of the final frequency then you can take my circuit and add

schematic

simulate this circuit

If you're using CMOS, the delay can be a simple RC.

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  • \$\begingroup\$ You should try simulating this circuit. It gives you a symmetrical divide-by-three, not the 2/3 the OP is asking for. \$\endgroup\$ – Dave Tweed Mar 11 '15 at 23:38

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