PIC18F26K20 cannot set internal oscillator to high speed

Question

I have a project using a PIC18F26K20, and I am trying to use the internal Oscillator at 16 MHz. But no matter what I do it always runs at 32 kHz. My configuration is:

#pragma config FOSC = INTIO67               // Internal Oscilaor RA6 RA7 ports
#pragma config WDTEN = OFF                  // Watchdog Timeer disabled  
#pragma config HFOFST = ON                  // HFINTOSC Fast Start-up:
#pragma config PWRT = OFF                   // Power-up Timer Enable bit: OFF
#pragma config FCMEN = OFF                  // Fail-Safe Clock Monitor Enable bit:
#pragma config IESO = ON                    // Internal/External Oscillator Switchover bit ON

in code:

OSCCON=0xf7;                    // Internal Oscillator Hi 
OSCTUNE=0x00;

Can anyone tell me what I am missing to set internal oscillator to 16 MHz?

Answer 1

Here is how I set the internal oscillator to 8 MHz on the 18F24K22:

#include <p18cxxx.h>
#include "timers.h"

#define USE_AND_MASKS

#pragma config FOSC = INTIO67
#pragma config WDTEN = OFF
#pragma config XINST = OFF
#pragma config MCLRE = EXTMCLR
#pragma config LVP = OFF

void main (void)
{
    // set internal oscillator to 8 MHz
    OSCCON = 0b01100010;

Answer 2

According to Section 2.5.2 of the datasheet (page 32), HFINTOSC is enabled when:

• SCS1 = 1 and IRCF<2:0> 000
• SCS1 = 1 and IRCF<2:0> = 000 and INTSRC = 1
• IESO bit of CONFIG1H = 1 enabling Two-Speed Start-up.
• FCMEM bit of CONFIG1H = 1 enabling Two-Speed Start-up and Fail-Safe mode.
• FOSC<3:0> of CONFIG1H selects the internal oscillator as the primary clock

The HF Internal Oscillator (IOFS) bit of the OSCCON register indicates whether the HFINTOSC is stable or not

I'm not clear on why SCS1 =1 and IRCF<2:0> is listed twice.

#pragma config FOSC = INTIO67       // Internal Oscilaor RA6 RA7 ports
#pragma config WDTEN = OFF          // Watchdog Timeer disabled  
#pragma config HFOFST = ON          // HFINTOSC Fast Start-up:
#pragma config PWRT = OFF           // Power-up Timer Enable bit: OFF
#pragma config FCMEN = OFF          // Fail-Safe Clock Monitor Enable bit:
#pragma config IESO = ON            // Internal/External Oscillator Switchover
#pragma config SCS1 = 1             // select internal oscillator as system clock
#pragma config IRCF = 0             // 31 kHz device clock derived directly from LFINTOSC

main()
{
    OSCTUNE=0x00;
    OSCCON=0xf3;                    // Internal Oscillator Hi 
    while(HFOFST==0);               // wait for HFINTOSC to be stable

So I've add a couple of additional pragmas based on the instructions in Section 2.5.2. I also changed the first line of main to set OSCCON to 0xf3 instead of 0xf7, so it does overwrite the HFOFST bit. It then waits for that bit to become clear before doing anything else.

I think the setting of SCS1 may be the issue. It defaults to 0 and the instructions above say it should be 1.

Answer 3

I have not tried to do this in MPLABX having used MPLAB1DE 8.82 mostly. However be careful that there is not a conflict between the config bits which you can set up in an IDE menu and the pragmas that you have set at the top of the code as I am not clear which of the two it would default to.

From reading the datasheet available here: ww1.microchip.com/downloads/en/DeviceDoc/41303G.pdf

Page 3 says that "Software selectable frequencies range from 31kHz to 16MHz" Page 11 talks about these two features --> 1) "An internal oscillator block which contains a 16MHz HFINTOSC oscillator and a 31kHZ LFINTOSC oscillator which together provide 8 user selectable clock frequencies, from 31KHz to 16Mhz. 2) "A Phase Lock Loop (PLL) frequency multiplier available to both the high-speed crystal and internal oscialltor modes, which allows clock speeds of up to 64Mhz. Used with the internal oscialltor the PLL gives users a complete selection of clock speeds from 31KHz to 64Mhz - all without using an external crystal or clock circuit"

So if you now look at page 27 it details the different modes particularly HS High-Speed Crystal/Resonator and HSPLL High-Speed Crystal Resonator with PLL enabled.

Primary clock modes are selected by the FOSC<3:0> bits of the CONFIG1H Configuration Register.

I think this should help you; good luck!

p.s. (Figure 27 on page 39 contains a good timing diagram showing a Clock Switch Timing Transition from slow speed to high speed)