I know that entities can use unconstrained array types (such as
STD_LOGIC_VECTOR) in their port list, which will be automatically sized to match the signal connected in the port map when instantiated (and possibly different sizes for each instantiation). Within the entity attributes such as
'HIGH can be used to discover the actual instantiated range.
I have such an object, which is a parallel -> serial converter (accept any size input, wider inputs require more clock cycles to spit out).
Is it possible to make range inference work in reverse, that is, to have the range specified in a subcomponent, applied to an unconstrained signal in the parent component, and propagated from there to other components?
My application has a number of data source subcomponents producing data streams of various width, arbitration logic to sample and serialize these sources round-robin, and parallel->serial converters doing the actual serialization and handshaking with the bus arbitration logic.
Right now I have the signal widths specified as constants in a package, but this means whenever any stream data format changes, I have to change both the source subcomponent and the package. I'd really like for the width to be specified in the source component only, since the downstream components adapt to any width.