I am trying to write verilog code that will set the initial value of the output of a positive-edge triggered flip-flop to 0. The behaviour of the flip-flop circuit is exactly what I want AFTER the clock or the input c hits. Unfortunately, at the very beginning (before any activity in c or clk) the x value is wrong because my initial statement seems to have no effect:
I understand that the problem may be that the Q output of the flipflop is always initially 0, and the inverter sets the x value to 1. Therefore, could someone suggest how to change the code so that the initial value of x is 0? Maybe use a series of latches? Essentially, the behaviour I want is that when the c value is high, x is also high, but when the clock hits, x is always reset to 0.
module test (c, x, clk); input c; input clk; output x; reg x; initial begin x = 0; end always @(posedge clk or posedge c) begin if (c) begin x = c; end else begin x = 1'b0; end end endmodule