Verilog inital value for flip flop

Question

I am trying to write verilog code that will set the initial value of the output of a positive-edge triggered flip-flop to 0. The behaviour of the flip-flop circuit is exactly what I want AFTER the clock or the input c hits. Unfortunately, at the very beginning (before any activity in c or clk) the x value is wrong because my initial statement seems to have no effect:

I understand that the problem may be that the Q output of the flipflop is always initially 0, and the inverter sets the x value to 1. Therefore, could someone suggest how to change the code so that the initial value of x is 0? Maybe use a series of latches? Essentially, the behaviour I want is that when the c value is high, x is also high, but when the clock hits, x is always reset to 0.

module test (c, x, clk);
   input c;
   input clk;
   output x;
   reg x;
   initial begin
     x = 0;
   end
   always @(posedge clk or posedge c) begin
      if (c) begin
        x = c;
      end else begin
        x = 1'b0;
      end
   end
endmodule

Answer 1

You are using c as an active high reset, then setting the value to c rather than 1'b0. It is active high so c is always 1 when this code executes. The solution to this is the reset condition to 0 not c:

always @(posedge clk or posedge c) begin
  if (c) begin
    x <= 1'b0; //Reset Condition
  end else begin
    //x <= ...;
  end
end 

Your code makes use of an initial and asynchronous reset. This does not really represent any type of hardware you have to choose one or the other, you can not have both.

The waveform in the question does not show the async reset being applied at the start of the simulation. you should apply it for at least 1 clock cycle and release it on the posedge of your clock.

Answer 2

(Answering after 5 years; might get useful to someone like me.)

The schematic output from Vivado 2020.2 gives this schematic. So the problem seems to be according to schematic in question. Although the two schematics are functionally same, the functioning before inputs are applied isn't same.

Somehow, the Quartus (used in question) needs to be forced to utilize PRE instead of CLRN input for c. Accordingly, the following Code should work as desired in question with all simulators.

module test (input c, x, output reg clk);
   initial x = 0;
   always @(posedge clk or posedge c)
      if (c) x = 1'b1;
      else x = 1'b0;
endmodule