I am working with a SmartFusion2 FPGA, and I am trying to implement a fine delay line. For that, I would like to control exactly the content of some LUTs, to get cells with no logic properties but interesting timing variations. So, my goal is to describe few individual cells in VHDL and link them to more abstracted VHDL code. I am using Libero SoC v11.5.

My problem is that I cannot find a way to do that with Microsemi's tools. There is a macro library for the SmartFusion2, with a promising element: "ARI1", but there is two issues:

  1. I don't know how to explore or link that library to my VHDL code.
  2. The "ARI1" macro is the only one that is not listed in the IDE catalog under macro.

Any tips for gate-level design with the SmartFusion2 is welcome.


1 Answer 1


This kind of design is pretty uncommon, but you are on the right track. To do delay-line type work you will probably need to force both the instantiation of resources you've mentioned, and the placement, otherwise results may not be the same across tooling runs. You've then got the problem that the results will not be consistent across parts, and will be temperature dependant.

The only examples I've seen are in the Altera cookbook to create random number generators (picking up the background/shot noise) using chains of back to back inverters, one per LUT. See pages 102 of the cookbook and the file random/chain_delay_race.v in their zip. For this application the part/temperature variance doesn't matter and the injection point into the chains is changed during operation to force hazards to occur.

As you mentioned you'll need to find the cells from the vendor's macro library. Taking the part library you linked to, why not use INV and INV1 primitives? These look much simpler to wire in than ARI1. For simulation you'll have a simulation library provided by the vendor somewhere in the tools directory - you'll need to add the hunt around for the paths and add to your simulator's import list (not familiar with Microsemi tooling, sorry). I usually find them using grep -r [primitive] ~/tools/../ or similar over the tools dir :-/

Sometimes a good way to find example instantiations of primitives is to synthesise something high level in Verilog/vhdl then look at the generated netlists to see how it's done.

If your application needs a fixed delay on an input signal, did you notice the built in delay primitives - I see I/O pads have a INPUT_DELAY attribute, so you could perhaps tweak this to save resources?

  • \$\begingroup\$ Thanks! That cookbook is great, I will certainly need the latch circuit p103. The INV1 seems promising, and I can already add it. I think I will start here and get more experience with the tool-chain. I would like to use AR1 to reach resolution beyond 50ps. I cannot use the INPUT_DELAY attribute as I need dynamic delays. \$\endgroup\$
    – pserra
    Mar 16, 2015 at 19:49
  • \$\begingroup\$ Glad to help. I did spot the absence of programmable timing/delay clock units on the SmartFusion2 datasheets. Usually the DDR3 memory pins on fabric have programmable delay taps (for dynamic DQS calibration), but as it's a hard core on this device, they are unlikely to be directly accessible :-/ \$\endgroup\$
    – shuckc
    Mar 17, 2015 at 11:14

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