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I'm laying out a PCB for a project that has an HD-SDI input, which uses a 1.5GHz signal. I'm new to high-frequency considerations, so I'm struggling with a few concepts. Here is the schematic and layout of the area near the SDI input, which is based entirely off the recommended design of the chip I'm using. J2 is a 75\$\Omega\$ MMCX through-hole jack and the chip on the right is the Semtech GS2961A (SDI-to-parallel converter).

enter image description here

enter image description here
4-layer board
Red: Top layer
Blue: Ground layer and bottom layer

For reasons, I put the MMCX jack and the components on the same side of the board. Since the jack is through-hole, the SDI signal enters the board on the bottom layer and comes up to the top layer in a via (located to the left of R1). In order for the via to have the necessary 75\$\Omega\$ impedance, I had to make a large anti-pad around the via. Similarly, the width of the trace carrying the SDI signal is such that it also has a 75\$\Omega\$ impedance. So far so good.

The part that concerns me is how the anti-pad around the via affects the impedance of the trace as it approaches the via. Since the trace impedance is a function of its distance from its reference plane, what happens when that reference suddenly vanishes? Is there a sudden impedance spike that will cause reflections or is the effect negligible?

Also, should the ground plane be removed underneath the resistors (R1, R2, and R3) forming the termination circuit?

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    \$\begingroup\$ I think you're being excessively paranoid. Even at 1.5 GHz, one wavelength is 20 cm. Your traces are a tiny fraction of that, so transmission line effects of any sort are going to be negligible. You just need to make sure that the circuit overall is a good match to the coax at J2. \$\endgroup\$ – Dave Tweed Mar 13 '15 at 1:51
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    \$\begingroup\$ Although it's not the clock freq you want to use when considering the distance rather the rise time or frequency content of the edge rate. Still probably short enough to just be treated as lumped element. \$\endgroup\$ – Some Hardware Guy Mar 13 '15 at 4:55
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Yes you will have an impedance discontinuity there. You should also look at how the return current is going to flow where you have that via. That's another discontinuity there current travels in a loop so I would think about having a return path there. Don't know what your bottom layer is though.

Trying to find the impedance all the way through that structure would probably require a field solver. Personally I'd avoid the via if you can. My guess isn't will increase your insertion loss.

On the other hand that via is close (less than 1/4 wave length) to the connector so it will get lumped together with it.

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  • \$\begingroup\$ I wouldn't mess around removing plane under the resistors either. \$\endgroup\$ – Some Hardware Guy Mar 13 '15 at 1:49
  • \$\begingroup\$ If it was me, I would pour ground on the top and then put a via fence on the circumference of that signal via clearance. \$\endgroup\$ – scld May 15 '15 at 15:19

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