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I work on DE1-Soc. I am using a linux BSP (linux console) that i found in terasic's website linux image.

I have some questions about the AXI bridge. In fact i would like to send some data from the hps to the fpga through the AXI bridge ( HPS-to-FPGA AXI ) and then use those data by the FPGA. I created a Quartus project based on the DE1-SOC-GHRD. The DE1-SOC-GHRD includes the file soc_system.qsys which includes hps_0 (HPS component). I would like to use the EPCQ to store the fpga configuration (.sof) And sD card for linux and my app.

Can someone give me some advices about how to use the AXI bridge? work to do for the FPGA and work to do for processor?

I am new in Soc, and i found it hard to understand how it works. I read cyclone V handbook but i feel that i missed something and i don't know what.

update:

I used Qsys to generate my hps component ans my system. I created 2 slave component(read and write) ( avalon memory mapped slave) and i can through the lightweight HPS-to-FPGA bridge map the address of the first slave (write) and write data. Also with the second one i can read data from it by the hps. The problem is that the lightweight HPS-to-FPGA bridge has a capacity of 32 bits. So i would like to use the HPS-to-FPGA bridge which has a capacity of 128 bits. I did the same thing that i did for the lightweight. but it doesn't work. I don't know why??

What is the difference between those two bridges? is there something to add (configuration)? I didn't find the base address of the HPS-to-FPGA bridge? where can i find it?

for example: what I did for the lightweight bridge

first:

define HW_REGS_BASE ( ALT_STM_OFST )

define HW_REGS_SPAN ( 0x04000000 )

define HW_REGS_MASK ( HW_REGS_SPAN - 1 )

define WRITE 0x0

define READ 0x10


// lightweight base address

define ALT_LWFPGASLVS_OFST        0xff200000


virtual_base = mmap( NULL, HW_REGS_SPAN, ( PROT_READ | PROT_WRITE ), MAP_SHARED, fd, HW_REGS_BASE );

then:

// address for write

h2f_write=virtual_base + ( ( unsigned long  )( ALT_LWFPGASLVS_OFST + WRITE ) & ( unsigned long)( HW_REGS_MASK ) );

//address for read

h2f_read=virtual_base + ( ( unsigned long  )( ALT_LWFPGASLVS_OFST + READ ) & ( unsigned long)( HW_REGS_MASK ) );
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  • \$\begingroup\$ Have you looked into the design examples that comes with the board and those you can find on Altera's web site? I have not used DE1, but the other Cyclone V based SoC systems have a lot of example code, including the one for SD card access. \$\endgroup\$ – FarhadA Mar 17 '15 at 7:23
  • \$\begingroup\$ thank you for your response! i did some small projects but using the lightweight hps-to-fpga axi bridge . I didn't find a tutorial about the hps-to-fpga axi bridge. So i don't know how to configure it with qsys and how to map the slave address. i tried 0xc0000000 (hps-to-fpga axi bridge offset) + slave address but it didn't work... \$\endgroup\$ – Jalal Tellal Mar 18 '15 at 12:40
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the second you need to know is who are you (your future device): a master or a slave? An AXI master can initiate transactions but the slave cannot, it can only respond to a master initiation. while the first is what it is very probable that you (should) use the AXI as an IP block in your design therefore the cyclone handbook will not help you but the AXI IP block documentation, user guides, examples, etc... will.

typically, the FPGA development environment integrates the tool to inherit and configure various IP blocks. in altera quartus ii, MegaCore IP Library responds for this.

therefore my advice to you is to learn quartus deeper :-)

good luck.

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