I'm building a sixteen bit Carry Lookahead Adder for my EE class. I'm definitely a noob to all this so bear with me, however I've been googling for a WHILE and haven't found any answers.

Here is the code for the test bench. I KNOW this part is correct because it was given to us by the professor.

Here it is:

// Verilog test fixture created from schematic /home/alexx/Documents/ee101_xilinx/ee101_lab5_xilinx/ee101_lab5_cla/cla16.sch - Mon Mar 16 17:00:11 2015

`timescale 1ns / 1ps

module cla16_tb();

// Inputs
   reg C0;
   reg [15:0] A;
   reg [15:0] B;

// Output
   wire C16;
   wire [15:0] S;

// Bidirs

// Instantiate the UUT
   cla16 UUT (
// Initialize Inputs
   `ifdef auto_init
         initial begin
            A = 16’h0000; B = 16’h0000; C0 = 0;
            A = 16’h0000; B = 16’h0000; C0 = 1;

Here is the console output in iSim:


run 2000 ns

Simulator is doing circuit initialization process.

Finished circuit initialization process.

So not much help there.

I ran the "check schematic" tool on EVERY schematic associated and they all returned no warnings and no errors. The only thing different about this than the schematics I've made in the past is the use of user-created symbols. We're given a completed PG and we have to make our own CLL, use that to make a 4-bit adder, and combine those to make a 16-bit adder.

I am very, very frustrated by this.

I've attached a screenshot of the waveform, and I can attach screenshots of the schematics if necessary.

Please help me debug this.


iSim waveform


2 Answers 2


Don't assume it's good just because the professor gave it to you. If you haven't learned this already, you will learn this at some point. If you assume, you make an ass of u and me. VERIFY YOUR ASSUMPTIONS. To me, it looks like there may be some issues in the testbench.

Two things to try: initialize the regs to zero by adding = 0 right before the semicolons (e.g. reg C0 = 0;). Second thing to try is commenting out the ifdef/endif around the initial block (add // to the beginning of both lines).

If those don't work, isolate it by commenting out the entire UUT block and try again.

  • \$\begingroup\$ Definitely true. Thanks for the ideas, I'm trying them now. I guess I would just hope that the code I'm given is correct, but I shouldn't assume it! \$\endgroup\$ Mar 17, 2015 at 19:27
  • If you want to use ifdef auto_init, you must compile your testbench with defining auto_init. In modelsim you can use the following script to compile your testbench and define the parameter auto_init. (type the following script on Transcript instead of manual compile) :

    vlog cla16_tb.v +define+auto_init

  • However you can remove the statements ifdef auto_init and endif from the testbench and compile it without any additional definitions. (manual compile)

I simulated the following code (cla16.v) with your testbench with the two above methods and could get the correct result :

module cla16(A,B,C0,S,C16);
    input [15:0] A,B;
    input C0;
    output [15:0] S;
    output C16;
    reg [15:0] S;
    reg [16:0] C;
    integer i;
    always @* begin
        C[0] <= C0;
        for (i=0; i<16; i=i+1) begin
            S[i] <= A[i] ^ B[i] ^ C[i];
            C[i+1] <= ( A[i] & B[i] ) | ( A[i] & C[i] ) | ( B[i] & C[i] );

    assign C16 = C[16];
  • \$\begingroup\$ Thanks for the suggestions. I copy/pasted your code into the test bench and had the same results. So I added a `define auto_init line immediately prior to the ifdef line, and now the code won't run at all. It's throwing an error inside the ifdef block, saying there's a syntax error somewhere where I'm defining the inputs (not sure if that's the right terminology). Any ideas? I tried commenting out the ifdef/endif altogether but I still got the X's result. \$\endgroup\$ Mar 17, 2015 at 19:36
  • \$\begingroup\$ No, my code is for "cla16.v" not "cla16_tb.v". You must add a separate file to your project and copy my code inside it. Then use your testbench (cla16_tb) and define auto_init inside it before the module statement (`define auto_init). Finally you must compile cla16.v and cla16_tb.v and simulate the testbench to see the correct result. I did it and the results was correct. \$\endgroup\$
    – Amir
    Mar 18, 2015 at 3:58

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