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I want to compile and simulate this simple UVM example using Modelsim-Altera 10.1d tool.

 module uvm_first_ex;
 import uvm_pkg::*;
 `include "uvm_macros.svh"
 initial begin
   `uvm_info("ID","WELCOME TO UVM",UVM_MEDIUM);
 end  
 endmodule:uvm_first_ex

I get error when I try to compile the above code. But I have heard that UVM is supported by Modelsim except randomization. It would be helpful to me if anybody can suggest me something on this. Ofcouse I can use EDA playground but I was wondering how to do it in Modelsim-Altera while the same can be done on EDA playground using modelsim tool itself.

This is the error message I get :

** Error: G:/Verilog/uvm_ex1.sv(2): Could not find the package (uvm_pkg). 
Design read will continue, but expect a cascade of errors after this failure.
Furthermore if you experience a vopt-7 error immediately before this error then
please check the package names or the library search paths on the command line.  
** Error: G:/Verilog/uvm_ex1.sv(3): Cannot open `include file "uvm_macros.svh".  
** Error: G:/Verilog/uvm_ex1.sv(5): (vlog-2163) Macro ``uvm_info is undefined.  
** Error: G:/Verilog/uvm_ex1.sv(5): near "(": syntax error, unexpected '('
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  • \$\begingroup\$ What is your error message? Did you define $UVM_HOME and include +incdir+$UVM_HOME/src $UVM_HOME/src/uvm.sv in your vlog arguments? \$\endgroup\$ – Greg Mar 17 '15 at 17:14
  • \$\begingroup\$ NO ONE CAN HELP YOU DEBUG AN ERROR IF YOU DO NOT SHOW IT! \$\endgroup\$ – dave_59 Mar 17 '15 at 23:22
  • \$\begingroup\$ This is the error message I get : ** Error: G:/Verilog/uvm_ex1.sv(2): Could not find the package (uvm_pkg). Design read will continue, but expect a cascade of errors after this failure. Furthermore if you experience a vopt-7 error immediately before this error then please check the package names or the library search paths on the command line. ** Error: G:/Verilog/uvm_ex1.sv(3): Cannot open include file "uvm_macros.svh". ** Error: G:/Verilog/uvm_ex1.sv(5): (vlog-2163) Macro uvm_info is undefined. ** Error: G:/Verilog/uvm_ex1.sv(5): near "(": syntax error, unexpected '(' \$\endgroup\$ – Abhi Mar 18 '15 at 2:46
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Based on the error message, you are not including the UVM source in your compile. Some tools have UVM built-in that can be enabled with the -uvm argument at compile time (refer to the user manual).

Alternatively you can add +incdir+$UVM_HOME/src $UVM_HOME/src/uvm.sv as a compile time argument, where $UVM_HOME is the path to the UVM source. This method works even if your simulator does not include UVM, but does support SystemVerilog. You can download UVM (source and manual) at http://www.accellera.org/downloads/standards/uvm

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  • \$\begingroup\$ How do i do that? I wanted step by step procedure for it. \$\endgroup\$ – Abhi Apr 1 '15 at 4:15

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