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I'm using several Xilinx FPGAs and boards from Spartan3E up to KC705/VC707 and I'm very familiar with UCF files, but there is one question that bothers me...

Why does translate for Virtex-6 not know IOSTANDARD LVDS, but translate for Series7 does?

or

Should I use IOSTANDARD LVDS_15 on KC705 for sysclk instead of LVDS?

Here is the correct UCF snippet for a KC705 board's SystemClock:

##  Bank:           33 - VCC=1.5V (VCC1V5_FPGA)
##  Location:       U6 (SIT9102)
##      Vendor:     SiTime
##      Device:     SIT9102AI-243N25E200.0000 - 1 to 220 MHz High Performance Oscillator
##      Frequency:  200 MHz, 50ppm
NET "KC705_SystemClock_200MHz_n"    LOC = "AD11";               ## {IN} U6.5
NET "KC705_SystemClock_200MHz_p"    LOC = "AD12";               ## {IN} U6.4
NET "KC705_SystemClock_200MHz_?"    IOSTANDARD = LVDS;
NET "KC705_SystemClock_200MHz_p"    TNM_NET = "NET_SystemClock_200MHz";

And here is an accepted UCF snippet for a ML605 board's SystemClock:

##  Bank:           34 - VCCO=2.5V (VCC2V5)
##  Location:       U11 (SIT9102)
##      Vendor:     SiTime
##      Device:     SiT9102 - 1 to 220 MHz High Performance Oscillator
##      Frequency:  200 MHz, 50ppm
NET "ML605_SystemClock_200MHz_n"    LOC = "H9";                 ## {IN} U11.5
NET "ML605_SystemClock_200MHz_p"    LOC = "J9";                 ## {IN} U11.4
NET "ML605_SystemClock_200MHz_?"    IOSTANDARD = LVDS_25;
NET "ML605_SystemClock_200MHz_p"    TNM_NET = "NET_SystemClock_200MHz";

Normally, an I/O standard is associated with a voltage so STA can calculate the correct timings. Further more I saw many differential clocks feed into FPGAs with AC-coupling (e.g. from ICS844021I for SGMII).

But when we look into both schematics, we can't find an AC-coupling for sysclk:
- ML605 Schematic
- KC705 Schematic

Normally, I would say LVDS should be used if AC-coupled and LVDS_xx should be used if DC-coupled. But the KC705's UCF says the contrary.

Can anyone explain when LVDS should be used?

P.S.
1. The KC705 snippet is from KC705 master-XDC incl. IO standards
2. The ML605 master-UCF is shipped without IO standards

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Xilinx has been inconsistent with the LVDS iostandard, I won't delve into earlier generations than spartan-6!

First, LVDS is current based (3.5mA into 100 ohm, around 350mV swing) and is electrically the same whatever the bank voltage.

Spartan-6 supports LVDS outputs from a bank with a VCCO of 3.3 (LVDS_33) or 2.5 (LVDS_25). Since Virtex-6 doesn't support 3.3 banks, they only have LVDS_25 and kept the same nomenclature as the spartan-6 to prevent designer suicide.

Spartan-6 and Virtex-6 use VCCAUX (3.3 or 2.5 for spartan, 2.5 only for Virtex) for LVDS input and should be available on all banks whatever its VCCO (never tried it though, I've always put it on a matching VCCO bank).

Series-7 LVDS output requires VCCO to be either 2.5 on HR banks (LVDS_25) or 1.8 on HP banks (LVDS). Why they gave it the name LVDS instead of LVDS_18? Xilinx only knows. Again, they are the same electrically, but obviously the driver has to be different if they don't have the same VCCO.

Series-7 LVDS input requires VCCO to be 1.8/2.5 only if the internal termination is used. Other VCCO can be used for input (with some restrictions) as long as external termination is present. I'm guessing this is the case for KC705. I'm also guessing that for consistency (sigh), they expect LVDS_25 inputs on HR banks and LVDS on HP.

So, since series-6 we have LVDS a VCCO of 1.8, LVDS_25 for 2.5 and LVDS_33 for 3.3. Again, they are electrically the same, only the driver differs and the mechanism for internal termination.

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