SRAM swapped address / data bits

Consider the following wiring from a microcontroller to a sram chip:

uC        SRAM
A0    --> A3
A1    --> A0
A2    --> A1
A3    --> A2
A4    --> A4
..    --> ..
A15   --> A15


As you can see, some of the address bits are swapped.

So when it comes to reading / writing the memory, will there be no errors? For example:

Address Microcontroller    Address Chip        Contents
0000                       0000                H
0001                       1000                e
0010                       0001                l
0011                       1001                l
0100                       0010                o
0101                       1010
0110                       0011                !
0111                       1011                \0


So... from the microcontroller's side the addresses are all ascending, but as you can see in reality, the uC addresses various memory places in the sram.

Is this a problem? I think with ONE microcontroller using the memory: no, since the microcontroller can nevertheless fetch the data in proper order (even if its not doing this from outside observation). But I think, with two or more microcontrollers this could become a problem IF the address bits are not connected in the same manner.

Conclusion:

As long as each address is distinct from another, there will be no reading / writing problem. (Considering ONE microcontroller using the memory!)

And: As long as each data bit is distinct from the other data bits, there will be no reading / writing problem. (Considiering ONE microcontroller using the memory!).

So my final question is: is my understanding for this problem correct or am I missing something? I could not find something on the internet concerning this problem!

• I believe some cartridge systems used nonstandard ordering as a form of copy/reverse engineering protection. – pjc50 Mar 18 '15 at 16:34
• @pjc50: I don't think non-standard ordering would be particularly effective in that regard. It's possible some systems used it for that purpose, but I think a more likely reason for using a non-standard ordering would be to facilitate layout. – supercat Mar 18 '15 at 16:36
• SRAM usually OK. Some DRAM refresh schemes depend on accessing selected address locations within certain periods. Failure to do so causes loss of data. || I have seen systems with address or data bits reordered for various reasons. – Russell McMahon Mar 20 '15 at 14:59

Your understanding is correct.

An address is just an arbitrary label for a location. All locations are identical (from the PoV of the MCU), and as long as each MCU accessing the locations agree on what the labels mean (are wired the same) then it doesn't matter the slightest how you assign those "labels".

As long as you use the same wiring for putting data in as you use for getting data out, it's just numbers.

Imagine you can't count. Imagine you think the numbers go 0, 3, 2, 5, 4, 1 instead of 0, 1, 2, 3, 4, 5.

Your boss tells you to put this box on shelf 3. So you go and put it on what you think is shelf 3, but it's actually shelf 1.

Later that day the boss tells you to go and get that box back off shelf 3 for him. So you go to what you think is shelf 3 (really shelf 1) and get the correct box.

Now, if the boss were to go to get the box instead he'd find a completely different box, because he didn't go to your shelf 3 but to his shelf 3 (your shelf 5).

• Is this ever used in actual circuits? I can imagine the flexibility to route the address and data lines however you want would be very helpful. – Austin Mar 18 '15 at 16:38
• It can be, yes. As long as you're not sharing the data there is absolutely nothing to stop you assigning the address pins as you see fit. – Majenko Mar 18 '15 at 16:39
• Have you ever seen this used in an actual product? – Austin Mar 18 '15 at 16:42
• One case where it wouldn't work (without some careful thought!) is certain EEPROMs where you must write specific data to specific addresses before programming a page... – Brian Drummond Mar 18 '15 at 16:44
• It wouldn't. I'd count that under the heading of "sharing the chip" - you're sharing control of the addresses between the MCU and the internal address counter. That is doomed to failure. The internal address counter would be your boss who can count. – Majenko Mar 18 '15 at 23:44

For many kinds of chips, especially asynchronous static RAM chips, the arrangement of address, and the arrangement of data bits, are entirely arbitrary. Indeed, while manufacturers will generally number the address and data wires to match the pinouts of other devices, the sequence of wires within the chip may have no relation to their numbering. Some kinds of chip, however, attach special meaning to certain addresses or address bits. Flash chips, for example, will often require that software wishing to write data must first perform a certain sequence of write operations before doing so; if the address or data bits were rearranged, the required sequence of writes could need to be modified accordingly. Also, if the pins for something like an EPROM are rearranged on a board, then one will either have to rearrange the pins on any device that is used to program it, or else shuffle around the bits in the file to be loaded.

• For sequential access flipping address bits around may cause a large increase in power consumption, if the flips will cause the SRAM to access new rows more frequently.
• If an SRAM module does not cover the entire addressable range (e.g. say the module has 768x128 bits), then a reordered address may cause you to accidentally address non-existing memory locations.

Otherwise the values/logic does not change as long as read and write use the same address reordering.

• Why would SRAM have rows in the first place? – Dmitry Grigoryev Apr 18 '17 at 10:59

In this context it's interesting to know that TI labeled the pins of the data and address lines of the TMS 9900 in opposite order to how it is usually done:
A0 and D0 were the most significant bits of the address and data word.