I'm doing a project for school where we need to select an ADC based on a variety of requirements. Two of these requirements, analog range and dynamic range, seem redundant to me.

From what I understand, the analog range is the voltage range of the analog input signal. However, the dynamic range is amplitude of a signal able to be handled, which seems synonymous to the analog range.

What is the distinction that I'm missing? I'm a bit confused because based off of this question, it seems like you can derive the dynamic range from the analog range.

  • \$\begingroup\$ A simplistic analogy is that dynamic range is what is the quietest thing you can here given a loud background noise (which is why people have to shout in clubs). Whilst analog range is how loud a sound needs to be to make you go deaf. \$\endgroup\$
    – Aron
    Commented Mar 19, 2015 at 16:49
  • 3
    \$\begingroup\$ To simplify the answers below, the analog range defines the range of the input side of the ADC. This can be 0->5V, 0->10V, -10->10V, -5->5V, 4->20mA, etc. The dynamic range of the ADC is defined by its bitness -> 10bit, 12bit, 16bit, etc. This defines the output of the ADC. The input signal (over a given analog range) maps to a digital output value (with a given dynamic range). The analog range should be selected to match the output signal of the device you wish to measure. The dynamic range is selected to give the required sensitivity for the application - higher is more expensive. \$\endgroup\$
    – J...
    Commented Mar 19, 2015 at 16:57

2 Answers 2


Dynamic range is defined as the difference (in dB) between the maximum input level and the noise floor of the ADC. This definition makes sense because it compares the max signal to a signal that is distinguishable above the noise. This is less than the Analog Input range because inputs close to LSB level that are in the input range can't be distinguished from noise and so are not in the dynamic range.

Defining dynamic range to the LSB is overly optimistic because no real-life ADC can actually resolve to the LSB level without extensive signal processing (if at all). In other words, driving the input with a perfect DC source will result in several output codes around a mean value (this is called Code Transition Noise).

Assuming for the moment, that the noise floor is negligible (it never is), then 6.02*n + 1.76 (dB) is an upper bound. e.g. n=10 => 61.96dB. BTW that formula is just the dB (log) representation of the max signal to quantisation noise ratio \$20*log_{10} \dfrac{max\_input\_rms}{quantisation\_noise\_rms}=20*log_{10}2^n+20*log_{10}\sqrt{3/2}\$

However, noise is never negligible, so typically the dynamic range is lower than this max value. If you convert measured dynamic range defined in this way, back to effective bits, that is the definition of Effective Number of Bits (ENOB).

Dynamic Range can also be usefully defined as SFDR, Spurious Free Dynamic Range as shown in the diagram below. This is defined as the difference (in dB) between the maximum input level and the largest spur in the FFT. This definition gives the maximum range in which a signal can be identified above harmonics and spurs, and is useful in communications applications. The diagram shows the SFDR (left) can be reduced by dithering (right). For more info see the referenced article (or ask another question).

Put simply, signals below the SFDR may be in the analog input range but not in the dynamic range by this definition.

(ref: ADC Input Noise)

enter image description here


The dynamic range of an ADC is the ratio of the biggest signal it can handle to the smallest signal it can resolve. For example, a 10 bit ADC resolves the input range into 1024 chunks. If the actual input voltage range is 0V to 1.023 volts then each chunk is 1 mV.

Maximum signal is 1.023Vp-p and minimum signal is 1mVp-p. The ratio is 1023 or in decibels this is about 60dB.

Formula: dynamic range is 20 \$log_{10}(2^n)\$ where n is number of bits

  • \$\begingroup\$ Hi can detecting signal below noise floor like using FFT or power spectrum accumulate can work for ADC? for example can the 1mVp-p limit above be reduced to 1uVp-p using FFT? \$\endgroup\$
    – Jtl
    Commented Apr 14 at 5:13
  • \$\begingroup\$ @Jtl I'm struggling to see how your comment applies the my answer and therefore why your comment is directed to me. If you have a query about ADCs there's no reason not to create a new post and provide more details and open the question to a wider audience. \$\endgroup\$
    – Andy aka
    Commented Apr 14 at 9:22
  • \$\begingroup\$ you are right, tnx \$\endgroup\$
    – Jtl
    Commented Apr 14 at 9:27

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