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I saw one schematic which uses an 8-bit shift reg to produce a sine wave with a resistor network.
I am guessing the resistors will be voltage dividers, but how are the values calculated? I tried to setup equations for different states but it looks like a mess with all the variables for resistor values.
The output voltage is fairly easy to calculate as:
$$ V_{output} = \sum_i\frac{V_iR_p}{R_i} $$
Where \$V_i\$ is the voltage at \$Q_i\$, and \$R_i\$ is the resistance connected to \$Q_i\$, and \$R_p\$ is the parallel connection of all the resistors.
Explanation:
Using superposition the output voltage can be calculated for one source at a time and summed using resistive division. In the following \$R_{pxi}\$ represents "all resistors in parallel except \$R_i\$" : $$ V_{output} = \sum_i\frac{V_iR_{pxi}}{R_i + R_{pxi}} $$
Another way to express all resistors in parallel (\$R_p\$) except \$R_i\$ is:
$$ \frac{1}{(1/R_p-1/R_i)} $$
So we have: $$ V_{output} = \sum_i\frac{V_i}{R_i + 1/(1/R_p-1/R_i)}\frac{1}{(1/R_p-1/R_i)} $$
Luckily, the above expression reduces to: $$ V_{output} = \sum_i\frac{V_iR_p}{R_i} $$
I don't think it gets easier than that.
Calculate the effective resistance of all the resistors but the first one in parallel. The contribution of the first output may be figured by taking the ratio of its resistor to the effective resistance of all the others in parallel. Then figure the effective resistance of all the resistors but the second one, and figure the ratio between that resistance and the second. Then do likewise for the third and fourth. The fifth, sixth, and seventh are symmetrical to the first three, so there's no need to repeat those calculations.
To figure the output voltage at any given time, add together the contributions from all of the outputs that would be high at that time. Because the output impedance is constant, the circuit will behave relatively linearly and so the voltage when e.g. the first three outputs are high will be equal to the sum of the voltages that would be present if only the first was high, if only the second were high, or if only the third were high.
First, the circuit is suspicious, as shown, because it does not have anti-lock circuitry. Ring counters can get into incorrect states and need to be forced back to the stable state using a reset or similar. That is why most circuits of this nature use the CD4018B which is specifically for creating ring counters. Lancaster discusses this in the CMOS cookbook. Excerpts online at http://support.karat-service.net/Unsorted/service-manuals-datasheets-4/schematics-42/info-424/Generators/Generators/Digital_Sine_Wave_Generation.pdf along with some other nifty ideas. Also, this actually answers the original question of how to calculate the values (in general).
