I am designing a \$\Sigma\Delta\$ ADC. Most of the high level specs are already set:
- order = 2
- 1 bit quantizer
- OSR = 256 (or 512 if needed)
- signal band: 100/200Hz
We expect some 16bit output, i.e. about 100dB SNR.
I have already carried some preliminary simulations with an ideal modulator, ideal integrators and switches (that's a switched cap circuit), and so on.
We are particularly concerned about DC and limit tones. As you maybe know, when a \$\Sigma\Delta\$ modulator is fed a DC signal it produces a periodic waveform and for some inputs the period may fall in the signal band, destroying the SNR around its frequency. Unfortunately this problem seems to be ignored by most of the papers that I have found and I am hoping to get some nice inputs from you.
We know we can use dithering to eliminate limit cycles but I'd love to use it only if necessary and I would like also to have some simulated (or calculated or whatever) proof of its effectiveness before this thing goes on the silicon.
The question then is: is there any standard technique to analyze a modulator robustness regarding limit cycles, and how can I get some quantitative results about it?
note: we're concerned about DC because the converter will be used with flow sensors, their output is "stairs-like" with very long steps, i.e. it stays stable for quite some time, it makes a small step, and so on.