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I am designing a \$\Sigma\Delta\$ ADC. Most of the high level specs are already set:

  • order = 2
  • 1 bit quantizer
  • OSR = 256 (or 512 if needed)
  • signal band: 100/200Hz

We expect some 16bit output, i.e. about 100dB SNR.

I have already carried some preliminary simulations with an ideal modulator, ideal integrators and switches (that's a switched cap circuit), and so on.

We are particularly concerned about DC and limit tones. As you maybe know, when a \$\Sigma\Delta\$ modulator is fed a DC signal it produces a periodic waveform and for some inputs the period may fall in the signal band, destroying the SNR around its frequency. Unfortunately this problem seems to be ignored by most of the papers that I have found and I am hoping to get some nice inputs from you.

We know we can use dithering to eliminate limit cycles but I'd love to use it only if necessary and I would like also to have some simulated (or calculated or whatever) proof of its effectiveness before this thing goes on the silicon.

The question then is: is there any standard technique to analyze a modulator robustness regarding limit cycles, and how can I get some quantitative results about it?

note: we're concerned about DC because the converter will be used with flow sensors, their output is "stairs-like" with very long steps, i.e. it stays stable for quite some time, it makes a small step, and so on.

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    \$\begingroup\$ Search for papers (late 80s, early 90s) by Bob Adams or Malcolm Hawksford, probably in JAES. From memory, limit cycles were a problem in 3rd or higher order, but I wouldn't trust that memory at this stage... \$\endgroup\$ – Brian Drummond Mar 20 '15 at 10:06
  • \$\begingroup\$ How about a form of dithering that adds a simple periodic waveform to the analogue input then subtract it in software/code after conversion. Is this technique useful because it seems quite intuitive that it would work as a form of dithering. Obviously choose a dither signal above or below the band of interest. \$\endgroup\$ – Andy aka Mar 20 '15 at 10:29
  • \$\begingroup\$ @Andyaka that is the first option, but dithering decreases SNR (and takes space and time of course), so I'd like to implement it only if it's necessary (and sufficiently effective). \$\endgroup\$ – Vladimir Cravero Mar 20 '15 at 10:33
  • \$\begingroup\$ I thought dithering+oversampling could be used to increase SNR? \$\endgroup\$ – pjc50 Mar 20 '15 at 10:38
  • \$\begingroup\$ well at least if you add a signal you limit the dynamic range, thus loosing some bits. If that's useless there's no point in implementing it. \$\endgroup\$ – Vladimir Cravero Mar 20 '15 at 10:41
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DC inputs to sigma-delta modulators naturally produce idle tones because the equivalent DC input can not be resolved to a standard +1, -1 pattern.

For example a 2nd order sigma-delta with a 1 bit quantiser (+1,-1 i.e \$\Delta\$=2) with a DC input of \$\dfrac{1}{256}\$ shows the output sequence repeating every 1024 cycles.

Empirically, the idle tones for a second order sigma-delta have been found to occur at frequencies as follows (where \$|A_{dc}|\$ is the dc input level magnitude): $$f_0=\dfrac{nf_s|A_{dc}|}{2\Delta}$$

In addition to tones for DC inputs; 3rd order modulators and higher can produce idle tones that appear to occur at random, even for dynamic, inputs.

My experience on working with sigma-deltas is that LC/idle tone generation is treated extensivley in the literature. For an authoritative treatment of LC and dithering, and plenty or references (86 relevant ref's), it's worth reading "Quantization errors and dithering in ΔΣ Modulators", S. Norsworthy; Ch3 of Delta-Sigma Data Converters:Theory, Design, and Simulation

I should also add that discussing this many years ago with a very experienced designer (Bob Adams), the only reliable method to determine the LC / idle tone problems (without actually building it), is to simulate; making sure to include all non-linearities, esp. in the Op-amps and to run the sim for as long as is practicable for your simulation hardware.

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  • \$\begingroup\$ Thanks for your input. I will read the chapter as soon as I'll be back at the university. Have you some literature about that empiric formula? Will I find it in the book? If I understand correctly I can use that formula to calculate the lowest possible input that will not cause an in band tone, correct? Thanks again for your advice, it is very precious to me. \$\endgroup\$ – Vladimir Cravero Mar 22 '15 at 13:30
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    \$\begingroup\$ You can find that in Ch3 of the referenced book. Good Luck. \$\endgroup\$ – akellyirl Mar 22 '15 at 14:05

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