I am using atmega16, and i need to use ADC feature in my project. As i know that there is a formula to set flag register ADPS2, ADPS1, and ADPS0. Which is used for determine the division factor between the XTAL frequency and the input clock to the ADC. But i don't know, which one the best division factor i need. How to determine? Should i use division factor 2, 4, 8 or?
As per the datasheet, the ADC must be used with a clock between 50 and 200kHz in order to get accurate results. Too fast and the S+H circuitry won't fully charge. Too slow and the S+H circuitry will discharge before the conversion is complete.
You must choose a prescaler that reduces the ADC clock from the clock control unit to this range. For instance, with a 8MHz system clock a factor of 64 will reduce the clock to 125kHz.