2
\$\begingroup\$

NMOS Gate

In this picture, when v1 and v2 are 0, M1,M2 are on and M3,M4 are off. V_T(threshold) = 1.7V, V_DD = 5V.

Why is it that M1 and M2 are ON under these conditions? I thought when there is no power through the gate the MOSFET will be off. Is it because M1, M2 are p-channel and M3, M4 are n-channel.

PS: This is an introductory EE course. So I'd really appreciate it if you please kindly keep your answer on n00b level.

\$\endgroup\$
2
\$\begingroup\$

Is it because M1, M2 are p-channel and M3, M4 are n-channel.

Yes.

You answered your own question. In fact, you probably meant to say "PMOS" in your question title, since that is the type of transistor gate function you are confused about.

V_threshold is a physical concept

To keep it simple, just consider the source and the gate. The threshold voltage is defined as the difference between them. When they are different, mobile charges are attracted into the channel and it becomes conductive (e.g. "on"). Without a difference in gate and source voltages, mobile charges stay away (the depletion region) and the channel is not conductive as a result (e.g. "off").

With v1, v2 = 0, The sources are near VDD, but the gates are 0. That creates a big difference between source and gate for the PMOS -- so they are "on".

but for the NMOS, the sources are 0 so with the gates also 0, there is no difference and the NMOS channels are "off".

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.