I am currently working on a design in which one of my ICs specifies the use of a 50 ohm trace. The answer to this question, Characteristic impedance of a trace, shows that a 120 mil trace is required to get this impedance.

The IC only has room for 18.8 mil traces, and that is assuming no space between traces. So, how can I actually design with that trace impedance kept in mind? Obviously I can decrease the board thickness or increase the copper height, but only to some extent and I would like this to be fabricated for somewhat cheap. How is this usually dealt with?

The IC that I am using is the MAX9382 which can operate up to 450 MHz, I will probably be using it around 400-450 MHz. The data that is being used is initially analog, but has to be hard limited to become digital in order to be used with that IC.

  • \$\begingroup\$ Post the PCB stack up and dielectric permittivity. \$\endgroup\$ – Mark Jun 29 '11 at 14:52
  • \$\begingroup\$ @Mark the stack up and dielectric permittivity are still up for discussion as to what to use (as in I am open for suggestions). But for FR-4 at 500 MHz the dielectric permittivity is 4.35 and a 63 mil board with 2 oz copper that results in 1.8 mil height \$\endgroup\$ – Kellenjb Jun 29 '11 at 14:58

Use a 4 layer stackup.

Calculating the trace width needed is pointless unless there is a solid ground plane under it, with a 2 layer design you may need to route traces on the other side which then pretty much ruins your impedance if they come anywhere close to your trace.

At 450Mhz you really should have solid, continuous, properly decoupled power and ground planes. This will improve noise performance, EMI issues, give you better impedance control, etc. Fabbing a 4 layer board isn't that much more to expensive than a 2 layer.

Use a 4 layer like:

>----------------Signal 1
8.3 mil
39 mil
8.3 mil
>----------------Signal 2

Spacing could change a little based on your copper thickness choice.

That will give you something like 10-20mil for your 50ohm trace on Signal 1/2 depending on final dielectric and copper thickness on the Signal layers.

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    \$\begingroup\$ this design is going to be simple enough that I can easily get a solid ground plane with no traces slicing it up. I do agree that having both a power and ground plane helps lots though. Not to mention the shorter distance between the layers. \$\endgroup\$ – Kellenjb Jun 29 '11 at 15:40
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    \$\begingroup\$ The PCB manufacture that I use says 9.3 mil between inner layer and top layer, 1.35 mil height for 1 oz copper, and from what I can find the relative permittivity is about 3.2. This makes my required trace width to be 18.55 mil. That sounds much more reasonable for a trace width. \$\endgroup\$ – Kellenjb Jun 29 '11 at 16:17
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    \$\begingroup\$ @Kellenjb Sounds about right, general rule of thumb is to stay under 10mil between the signal layers and the ground/power plane. In my experience its best to go with what the fab recommends, they all seem to assemble a bit differently and its not worth fighting them unless you have a good reason. Keep in mind that with 10-20mil traces you'll probably lose ~2-3 ohms of impedance from the soldermask so you may want to shoot for more like 52-53 ohms, or ask the fab for the thickness and dielectric constant of the mask and include it in the calculation. \$\endgroup\$ – Mark Jun 29 '11 at 19:02

You don't have to worry about the impedance of very short PCB traces as part of a longer trace. So you will have a thinner trace directly next to the chip. But if the trace has to go any distance, then you need to adjust the thickness of the trace as it gets away from the chip. You will just "fan out" the trace width away from the chip. That is how I have always seen it done.

This is not unlike the connectors of any transmission line. The impedance of a single short element might be a little less, but it is slight when compared to the overall transmission line.


Often having overly wide traces can cause issues with the capacitance of the trace. Making the trace thinner will reduce the capacitance. Of course having thinner traces messes up the impedance.

If the PCB stackup is done differently, where the signal layer is closer to the power/gnd plane, then the trace can be thinner while still having the proper impedance. On a multilayer PCB this only works when the signal is also on an inner layer-- making it difficult to have the proper impedance AND capacitance on an outer layer.

The end result is that it's all a compromise. I usually run those signals on inner layers with optimized PCB stackup's-- but then keep the traces skinny and very short when it has to go to an outer layer to get to a chip.

On a 2 layer PCB it's very hard to have the proper impedance on narrow traces-- so I usually don't bother. If impedance is critical I will go to at least a 4 layer PCB.

  • \$\begingroup\$ By definition when you are looking at your impedance you are looking at a relative measure of capacitance to inductance. The fact that the trace has to be that wide is a sign that the distance between the ground plane and the trace is great enough for the capacitance not to be that great. Think about the space you need between traces to not have coupling! \$\endgroup\$ – Kortuk Jun 29 '11 at 14:19
  • \$\begingroup\$ @Kortuk That's not strictly true. I just went through the calculations for a board that I just did. Layer 3 is a plane. For 50 ohms, a trace on layer 1 needs to be 21.81 mils and on layer 2 needs to be 8.03 mils. That L1 trace has 1.697pF/inch, while the L2 trace has 1.354pF/inch. That might not sound like a lot, but it's 25% more pF for layer 1-- and I've seen this have an influence on very high speed signals (>500 MHz). \$\endgroup\$ – user3624 Jun 29 '11 at 14:46
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    \$\begingroup\$ if you are changing from internal to the board to external to the board you are going to have your design equations change. If it is internal to the board and has two ground planes there are even closed form solutions. When designing RF circuits there were three primary concerns with impedance, is it matched, will it have to vary(vias and such), and will it have too much fringing to match my designs. Often with very wide traces you run into non-ideal situations, especially with coupling to nearby traces. I can say that even with wide traces(and I mean very wide) it still worked. \$\endgroup\$ – Kortuk Jun 29 '11 at 15:00

Can you route adjacent reference trace along with your signals? I've been told that routed triplets, or even quints if you can't fit triplets, etc. can sometimes work in situations like yours if you don't have a close plane to reference to. If you have a diff pair then it might be more like a quad, with adjacent references/returns outside on both sides of the diff pair. The same mentor suggests that a two layer board should be treated as two unrelated boards due to space between the layers, and routed references/returns are the way to go if more layers can't be had.

I was wrong about the quad for a diff pair. My notes from the relevant presentations say to use a triplet, with a reference BETWEEN the two signals of the diff pair. Still looking/waiting for impedance calculations this way. I'm told he's looking to find which RF/Microwave book they are in, he has a number of them.

  • \$\begingroup\$ @user4849, This is excellent advice. If you cannot get near the ground plane bring the ground reference to you! Do you have any references to design equations for this type of layout? This sounds both functional and exactly what the OP needs!\ \$\endgroup\$ – Kortuk Jun 30 '11 at 12:46
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    \$\begingroup\$ I don't yet. I just happened to have begin learning about this kind of thing about a week ago. I have requested a couple days ago a reading list and equation information such as you ask about, but have not yet seen a reply. I'll post here when I do. \$\endgroup\$ – billt Jun 30 '11 at 19:23
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    \$\begingroup\$ There were 4 long talks at Freescale FTF about this exact topic, the first one by Dan Beeker is maybe the most directly related here. PDF of slides is on freescale site, I think as Enabling Tech category, I'll post when I manage to find a link or filename to these too. Rick hartley also spoke, and one of his suggested books is free online thehighspeeddesignbook.com \$\endgroup\$ – billt Jun 30 '11 at 19:35
  • \$\begingroup\$ @Billt, I look forward to hearing back from you! \$\endgroup\$ – Kortuk Jun 30 '11 at 20:22
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    \$\begingroup\$ this one has "automotive" in the title. Check it out regardless of you application. Talks about things somewhat slower speeds than the previous guys. FTF-ENT-F0174 High-Frequency System Design (Part 3): Solutions for EMC Issues in Automotive System Transmission Lines [link]freescale.com/webapp/… \$\endgroup\$ – billt Jul 2 '11 at 4:31

First figure out if it's a real requirement. Over what distance must this be kept to? If it's a seriously high speed signal (look at the edge-rate compared to the length of the trace) you may need to perform some simulation. The Howard and Johnson reference that is in the answer to your linked question is a great resource on this sort of thing.

If the requirement is real, then figure out much tolerance there is (your board fab can probably only get to +/- 10% of what you ask for, so take that into account).

EDIT: Looking at your part you've now posted, you are in "real requirement" territory.

80ps edges are pretty quick! The "knee frequency" at which the harmonic start to drop off rapidly is upwards of 6GHz. Assuming propagation delay is about 66% of speed-of-light, 80ps is 16mm. The rule-of-thumb is that anything longer than 1/4-1/6 of the transition time is going to need to be treated like a transmission line, which means any trace longer than a few mm!

I'd hesitate to attempt this on a 2-layer board over any difference without doing some simulation.

You'll likely have to go multilayer to get the reference plane closer to the trace which allows thinner traces to meet the impedance specification. (EDIT: As pointed out in the comments, you could do it in 2 layers, but you'll have a really thin board then!)

Alternatively, you might be able to build a coplanar waveguide structure on 2 layers which can provide the impedance you are looking for. Or maybe increase the termination resistance, which means changing the trace impedance to match, which means a thinner trace. AppCAD can help you play with parameters for these options.

Sounds like fun :)

  • \$\begingroup\$ I think this is just telling the OP, if you really are asking this question you are out of luck and need a different PCB. Why multilayer, why not just thinner? \$\endgroup\$ – Kortuk Jun 29 '11 at 14:15
  • \$\begingroup\$ @Kortuk If the OP needed a 120mil trace for 50 ohms, he's probably using a 2 layer PCB that's about 63 mils thick. To get 50 ohms with 18 mil traces the separation between layers needs to be in the neighborhood of 10 mils, making that 2 layer PCB about 15 mils thick-- way too thin for most applications. Thus... Going with at least a 4 layer PCB is the way to do it. \$\endgroup\$ – user3624 Jun 29 '11 at 14:54
  • \$\begingroup\$ @DavidKessner, That was a secondary point to my comment, I thought it could use some explanation in the answer. \$\endgroup\$ – Kortuk Jun 29 '11 at 15:02
  • \$\begingroup\$ @Kortuk From the numbers I've seen in the past, building a 4 layer board that is a standard thickness such as 63mil is cheaper than building a 2 layer board at a non-standard thickness. \$\endgroup\$ – Mark Jun 29 '11 at 19:08

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