Impedance Matching and Large Trace Widths

Question

I am currently working on a design in which one of my ICs specifies the use of a 50 ohm trace. The answer to this question, Characteristic impedance of a trace, shows that a 120 mil trace is required to get this impedance.

The IC only has room for 18.8 mil traces, and that is assuming no space between traces. So, how can I actually design with that trace impedance kept in mind? Obviously I can decrease the board thickness or increase the copper height, but only to some extent and I would like this to be fabricated for somewhat cheap. How is this usually dealt with?

The IC that I am using is the MAX9382 which can operate up to 450 MHz, I will probably be using it around 400-450 MHz. The data that is being used is initially analog, but has to be hard limited to become digital in order to be used with that IC.

Answer 1

Use a 4 layer stackup.

Calculating the trace width needed is pointless unless there is a solid ground plane under it, with a 2 layer design you may need to route traces on the other side which then pretty much ruins your impedance if they come anywhere close to your trace.

At 450Mhz you really should have solid, continuous, properly decoupled power and ground planes. This will improve noise performance, EMI issues, give you better impedance control, etc. Fabbing a 4 layer board isn't that much more to expensive than a 2 layer.

Use a 4 layer like:

>----------------Signal 1
8.3 mil
>----------------Ground
39 mil
>----------------Power
8.3 mil
>----------------Signal 2

Spacing could change a little based on your copper thickness choice.

That will give you something like 10-20mil for your 50ohm trace on Signal 1/2 depending on final dielectric and copper thickness on the Signal layers.

Answer 2

You don't have to worry about the impedance of very short PCB traces as part of a longer trace. So you will have a thinner trace directly next to the chip. But if the trace has to go any distance, then you need to adjust the thickness of the trace as it gets away from the chip. You will just "fan out" the trace width away from the chip. That is how I have always seen it done.

This is not unlike the connectors of any transmission line. The impedance of a single short element might be a little less, but it is slight when compared to the overall transmission line.

Answer 3

Often having overly wide traces can cause issues with the capacitance of the trace. Making the trace thinner will reduce the capacitance. Of course having thinner traces messes up the impedance.

If the PCB stackup is done differently, where the signal layer is closer to the power/gnd plane, then the trace can be thinner while still having the proper impedance. On a multilayer PCB this only works when the signal is also on an inner layer-- making it difficult to have the proper impedance AND capacitance on an outer layer.

The end result is that it's all a compromise. I usually run those signals on inner layers with optimized PCB stackup's-- but then keep the traces skinny and very short when it has to go to an outer layer to get to a chip.

On a 2 layer PCB it's very hard to have the proper impedance on narrow traces-- so I usually don't bother. If impedance is critical I will go to at least a 4 layer PCB.

Answer 4

Can you route adjacent reference trace along with your signals? I've been told that routed triplets, or even quints if you can't fit triplets, etc. can sometimes work in situations like yours if you don't have a close plane to reference to. If you have a diff pair then it might be more like a quad, with adjacent references/returns outside on both sides of the diff pair. The same mentor suggests that a two layer board should be treated as two unrelated boards due to space between the layers, and routed references/returns are the way to go if more layers can't be had.

I was wrong about the quad for a diff pair. My notes from the relevant presentations say to use a triplet, with a reference BETWEEN the two signals of the diff pair. Still looking/waiting for impedance calculations this way. I'm told he's looking to find which RF/Microwave book they are in, he has a number of them.

Answer 5

First figure out if it's a real requirement. Over what distance must this be kept to? If it's a seriously high speed signal (look at the edge-rate compared to the length of the trace) you may need to perform some simulation. The Howard and Johnson reference that is in the answer to your linked question is a great resource on this sort of thing.

If the requirement is real, then figure out much tolerance there is (your board fab can probably only get to +/- 10% of what you ask for, so take that into account).

EDIT: Looking at your part you've now posted, you are in "real requirement" territory.

80ps edges are pretty quick! The "knee frequency" at which the harmonic start to drop off rapidly is upwards of 6GHz. Assuming propagation delay is about 66% of speed-of-light, 80ps is 16mm. The rule-of-thumb is that anything longer than 1/4-1/6 of the transition time is going to need to be treated like a transmission line, which means any trace longer than a few mm!

I'd hesitate to attempt this on a 2-layer board over any difference without doing some simulation.

You'll likely have to go multilayer to get the reference plane closer to the trace which allows thinner traces to meet the impedance specification. (EDIT: As pointed out in the comments, you could do it in 2 layers, but you'll have a really thin board then!)

Alternatively, you might be able to build a coplanar waveguide structure on 2 layers which can provide the impedance you are looking for. Or maybe increase the termination resistance, which means changing the trace impedance to match, which means a thinner trace. AppCAD can help you play with parameters for these options.

Sounds like fun :)