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I have a PIC18F2550 microcontroller on one board with three daisy chained 74HC595 chips. These are driving 7-segment displays and everything is working fine. 7-segment displays are connected with a cable. The thing is connected to my computer with USB. This is where it draws it power.

Then I added an another 74HC595 on a separate board to drive LEDs. It's not daisy chained with the other chips, but connected to separate pins on the microcontroller. These LEDs are sometimes on and sometimes off, might change state once when I try set them in different states from software, or not. Usually all of those LEDs end up being all on or all off. 7-segment displays continue to work as expected.

Then I added yet another 74HC595 on yet another board to drive a separate 7-segment display and connected it to separate set of pins on the micro. It functions the same way as the other separate board.

Schematic

Schematic shows the "main board". These 74HC595's are working correctly. The other two are connected the same way via pin strips (shown in the schematic as SV5 and SV6) and jumper cables.

Oh, and all the LEDs (including 7-segment display segments) have 1k resistors connected in series for current limiting. Here is a schematic of one of the other boards connected via SV5 and/or SV6 connectors. These are the ones which are not working correctly.

Second board schematic

I have tried slowing down the software side of sending bits to these shift registers with no luck. Everywhere it says that I shouldn't use long wires between chips. Is 10cm long? Should I add some decoupling capacitors or something to next to those non-working shift registers? Should I rather redo everything on one board? Is there an error in the design? Or what?

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  • \$\begingroup\$ How many bits are you shifting in before you assert the latch clock? \$\endgroup\$ – Tut Mar 24 '15 at 20:06
  • \$\begingroup\$ 8 bits then latch. I believe the software to be good, as it works with the 3 shift registers on the same board. \$\endgroup\$ – Mape Mar 24 '15 at 20:56
  • \$\begingroup\$ Since your output enables are tied to gnd (active) on your cascaded shift registers, it is preferable to clock 24 bits and then latch to avoid ghosting on your display. This is why I wanted you to double-check your clock count since you obviously don't want to clock 24 bits for a single 8-bit SR. \$\endgroup\$ – Tut Mar 24 '15 at 21:39
  • \$\begingroup\$ Ah, for the cascaded registers I am sending 24 bits and then latching. \$\endgroup\$ – Mape Mar 25 '15 at 20:46
  • \$\begingroup\$ In addition to Dwayne's suggestions, you might consider series resistors on your shift-register clock lines. Longer lines can cause reflections that are especially bad on clock lines (lines that use the edges) and can cause double-clocking. Something in the range 20 to 47 ohms will usually do it. \$\endgroup\$ – Tut Mar 25 '15 at 20:56
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Which pins on the micro did you connect the extra shift registers to?

Do you use separate routines to talk to each set of shift registers?

Things to check:

1) Short, heavy ground wire between the extra shift registers and the main board (with the micro on it).

2) decoupling capacitor(s) at the shift registers.

3) clock edge vs data change. You can safely change the data line and clock line at the same time so long at that clock edge is the NOT-active edge. That is: the clock line is going from HI to LO.

However, you must allow sufficient setup time for the data level before you assert the active clock edge (LO to HI).

Long wires can exacerbate this problem - the clock line has higher capacitance because you are feeding multiple chips. The data line feeds only one chip.

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  • \$\begingroup\$ Those "extra" shift registers are connected via SV5 and SV6 shown in the schematic. So, their data, clock and latch pins are connected to RC0, RC1, RC2 for one of them and RA3, RA4, RA5 for the other one. I did as suggested and added an (extra) heavy ground wire, a decoupling capacitor next to the shift register and played around with timings of data and clock pulses. No change. \$\endgroup\$ – Mape Mar 25 '15 at 20:51
  • \$\begingroup\$ Finally. Adding another decoupling capacitor brought it to life. \$\endgroup\$ – Mape Mar 27 '15 at 17:44

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