I am trying to create a components library in VHDL. I have many .vhd source files with different components. Ideally I would like to be able to instantiate them in a design using the same method as a standard library.(or similar)


library my_lib;
use my_lib.something.all;

And build a design using these components structurally. Ideally I'd like to keep these as separate files because there are attached custom symbol (bds) files associated.

The symbols only matter when using Active-HDL (10.1) Being able to pull these files in and use them in the block diagram file would be great!

I would be using Aldec Active-HDL(10.1), Xilinx Vivado(2014.2), and Altera Quartus (9.1 web).

Any help would be greatly appreciated.


Xilinx Vivado:

You can create/change the library a file resides in Vivado by clicking on the file, then clicking the button to the right of the Library label in the Source File Properties tab. You can create a library by assigning a file to a library that doesn't exist.

Altera Quartus II:

You can specify the library under Properties, for example: enter image description here You can also modify the Quartus II settings (".qsf") file for the project using set_global_assignment options.


You can move your component declarations into a VHDL package. This package is then loaded by a use statement.

A library can not be created by a file, but all tools - that I know of - have the ability to create a library in the project and assign files to them. Or some tools have a file property field to assign the selected file to a library.

If your intention is to spare component declarations in the architecture header, there is also a 'new' syntax to specify the full name of an entity:

myinst : entity mylib.myentity
  port map (

You just need to name the used library like the well known IEEE:

library mylib;

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