I am trying to create a components library in VHDL. I have many .vhd source files with different components. Ideally I would like to be able to instantiate them in a design using the same method as a standard library.(or similar)
library my_lib; use my_lib.something.all;
And build a design using these components structurally. Ideally I'd like to keep these as separate files because there are attached custom symbol (bds) files associated.
The symbols only matter when using Active-HDL (10.1) Being able to pull these files in and use them in the block diagram file would be great!
I would be using Aldec Active-HDL(10.1), Xilinx Vivado(2014.2), and Altera Quartus (9.1 web).
Any help would be greatly appreciated.