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I have two circuits which I have designed using verilog.One is Counter circuit and other is the debouncing pushbutton circuit.but I dont now how to instantiate a model so that the pushbutton circuit is also included in the main module of counter.Please help me.I am using a Digilent Basys-2 Spartan Board xc3s100e

 Counter Circuit
  module button_binary(
    input clock,
    input reset,
    input button,
    output led,
    output led2,
    output led3,
    output led4,
    output led5,
    output led6,
    output led7,
    output led8
    );

    reg [7:0]count;

    debouncing U1
    (
    .clock  (clock),
    .reset  (reset),
    .button  (button)
    );



 always @ (posedge clock or posedge reset)
   begin
    if (reset)
        count <= 0;
    else if (button)
        count <= count + 1;
    end

    assign led = count[0];
    assign led2 = count[1];
    assign led3 = count[2];
    assign led4 = count[3];
    assign led5 = count[4];
    assign led6 = count[5];
    assign led7 = count[6];
    assign led8 = count[7];
 endmodule 
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  • \$\begingroup\$ I think some more clarification of what you are trying to accomplish is necessary. From your question and the attached Verilog code, it is not readily clear to me if you want to achieve 1) a top level model with both a counter and debouncing module, or 2) a counter that has a debouncing module internally, or a debouncing circuit that has a counter internally. \$\endgroup\$ – Dr. Watson Mar 28 '15 at 14:10
  • \$\begingroup\$ I exactly want to include the debouncing module in counter module.The top module is the counter module. \$\endgroup\$ – raghav Mar 29 '15 at 3:59
  • \$\begingroup\$ OK, I understand now. So you'll want to instantiate the debouncing module within your counter module as I describe below. You may want to add a second code listing following the first that reflects any changes made since you asked the questions. That would help answer your follow-up questions on the warnings. \$\endgroup\$ – Dr. Watson Mar 29 '15 at 15:08
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I am not sure what you mean by main module, but I assume you mean that you are trying to include the debouncing module inside of your counter module??

If so, I would create two different verilog files, one with each module. In the counter module, to instantiate an instance of the debouncing module, you use the following syntax:

debouncing U0(
    .clock(clock_input_to_module),
    .reset(reset_input_to_module),
    .button(button_input_to_module),
    .out(out_output_from_module)
);

U0 is the name of the instance, and the variable names inside the parenthesis are wires and regs that you declare in the counter module. The names with the periods in front are the I/Os of the debouncing module.

Regardless though, if you need to instantiate a module, the above syntax is the method to do so.

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  • \$\begingroup\$ I am getting an error saying that "hierarchial block<denounce> is unconnected in core<button_binary> block \$\endgroup\$ – raghav Mar 29 '15 at 4:04
  • \$\begingroup\$ I get this error.WARNING:Xst:646 - Signal <out> is assigned but never used. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:1290 - Hierarchical block <U0> is unconnected in block <button_binary>. It will be removed from the design. \$\endgroup\$ – raghav Mar 29 '15 at 4:52
  • \$\begingroup\$ Please add your updated code so we can see the modifications. What XST is telling you is that in the top module, there is nothing being done with the <out> signal in the top module, perhaps it is not connected? Rather than waste space on your FPGA/ASIC with unused gates, it is optimizing unused parts out for you. \$\endgroup\$ – Dr. Watson Mar 29 '15 at 15:12
  • \$\begingroup\$ I have include the instantiated module(debouncing) in the top module right after the port definitions.Is it correct.Yes I will remove the out signal.See the code above I have updated as you have said. \$\endgroup\$ – raghav Mar 29 '15 at 16:59
  • \$\begingroup\$ For the hierarchical error, it mentions "donounce". Is that a spelling effort for debouncing? Also, you're not really doing anything with the debounching module at the top level, you are just feeding it input signals. You deleted the code for that debouncing module so I can't refer back to it, but XST might be optimizing out the debouncing module since it is not being used for anything. It is hard to tell though without being in front of the tool. \$\endgroup\$ – Dr. Watson Mar 29 '15 at 21:14

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