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In a load supply using P-MOS, the input to source is 25V. We found unfortunately that the MOSFET we chose and soldered has only 20V maximum gate-source voltage. Although there are voltage dividers consisting of R1 and R2, we are not sure upon the sudden turning on of NMOS, whether VGS could temporarily reach 25V, and whether the P-MOSFET Q1 could stand it. We haven’t yet found MOSFETs having rated VGS>20V yet. Questions:

http://www.diodes.com/datasheets/ZXMP6A17G.pdf

http://www.diodes.com/datasheets/ZXMP6A17G.pdf

  1. Could someone recommend PMOS having larger maximum VGS?
  2. The application of using PMOS for high voltage switch should be common and VCC=25V is unlikely to be at the high end of typical applications. So how do applications typically handle voltage exceeding maximum VGS?

Matt

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  • \$\begingroup\$ Usually when you're using that circuit, a few ms of time to turn on isn't a big deal. What exactly are you trying to do? \$\endgroup\$ – Matt Young Mar 29 '15 at 14:42
  • \$\begingroup\$ Still no details provided as requested :-( \$\endgroup\$ – Russell McMahon Mar 31 '15 at 18:03
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We can make this work well for you.
But attention must be given to the changes required.

You are trying to use the transistor in an unnecessary mode in order to attempt to eliminate a very common design requirement which simply needs to be faced.

ie you do not "need" a higher Vgs FEt - you just need to drive an otherwise suitable FET correctly by limiting Vgsmax to a voltage which is enough to drive the FET correctly worst case -but still less or much less than Vgs_absmax.

In addition, you need to specify switching speed requirements and address them explicitly as part of your design.

You ask (in a comment) "If we are using the PMOS for fast switching applications (~10μs),..." -> if you are using timings of the order of 10 uS (and you do not give any indication of switching speeds in your question) then the passive 30k R1 resistor is going to utterly mangle your switching waveforms. Without looking at the datasheet you can use a rule of thumb gate capacitance of 1 nF. That with 30k Rgs for turn off gives a time constant of 30 microseconds. Zener response times are far from your greatest problem.

Vgsmax of the MOSFET only needs to be safely greater than the maximum Vgs you need for full enhancement of the MOSFET under the worst case conditions of interest.
Very few MOSFETS need more than 12V Vgs to be driven as hard as is possible, so a Vgsmax rating of 20V is very acceptable.
By making R1 = R2 you reduce Vgsmax to about 12.5V.

Looks at data sheet ...

VGs of 10V (actually -10V) is the maximum you need to fully drive the FET worst case.
Gate capacitance appears to be comfortable under 1 nF. Better - use the gate charge curve at top right of page 6 to see what gate current you will need to remove the gate charge at the Vgs you wish to work at.
Note that they only specify Vgs up to 10V on this graph, and that gate charge is substantially higher at high Vgs levels.

"At a guesstimate", using 1k for R1 and R2 would probably achieve switching that is in the order of fast enough, and Vgsmax can probably be less than 10V allowing even smaller R1 - so lower RC time constant and less charge to remove as well.

It's not a marvellous GET - Rdson is 125 milliOhm typical at 10V Vgs, ~= 4A, 25 C. That mans you would get about 4 x 125 = 500 milliOhms Rds at 4A. That may be acceptable, but much better is possible at modest cost.


To design this driver possible we need to know:

Maximum switched current.
Switch timing waveforms - on or off for how long?, what rise & fall times needed and why?
What is the load? (resistive, inductive, heated filament, ...?) Anything else important that will change the question when we know about it.


Note that FET gate voltages want to be kept well away from Vgs_abs_max. The gate to channel interface is an oxide layer whose thickness is measurable in "atoms thick" and can be broken down by a whiff of overvoltage if unprotected. Driving with say 10V abs max and then providing a say 12V or 15V reverse biased zener connected gate to source and physically close to the FET. With a load with any inductance, adding this zener may transform reliability. This is because Millar coupling from Drain to gate can otherwise wreak overvoltage havoc on the gate oxide. (Ask me how I know :-) ).

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  • \$\begingroup\$ The answer is helpful and full of information, I appreciate it very much. I took quite some time to read every single points of the it. Could you address another two points: (1) "With a load with any inductance, adding this FET may transform reliability": (1.1)do you actually mean "adding this Zener"? (1.2)you are suggesting that inductance load possibly could cause voltage spike greater than VGS_MAX to break the "atom thick" layer? (2)[onsemi.jp/pub/Collateral/AND9093-D.PDF] "Millar coupling", are you referring to Miller Plateau? I think it is between S-G not D-G? \$\endgroup\$ – Matt Mitchell Mar 31 '15 at 17:06
  • \$\begingroup\$ @MattMitchell - Yes. Thanks, Answer amended. - "adding this zener" was intended. || I meant Millar coupling or Millar capacitance which occurs between Drain and gate. It is essentially caused by the small signal which couples D-g via the small physical capacitance being amplified in effect by the FET transconductance gain. (mA per volt). The effect is for it appear that a much larger capacitance exists. Inductive spikes in the drain circuit can and do couple into the gate and can drive Vgs to >> Vgsmax if precautions are not taken. \$\endgroup\$ – Russell McMahon Mar 31 '15 at 17:43
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Add a Zener diode from Source to Gate. This can either replace the resistor that you already have there or can be added in parallel with it.

Zener voltage is not critical - anywhere from 12 to 20 Volts is fine.

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  • \$\begingroup\$ If we are using the PMOS for fast switching applications (~10μs), does the Zener diode work to this speed? \$\endgroup\$ – Matt Mitchell Mar 29 '15 at 15:40

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