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I came across this figure in the datasheet for an accelerometer. It gives a very specific trace width (0.15mm) to escape from the pad, as well as a minimum length (0.5mm) at that width. So far, the only explanation I can come up with is thermal considerations during soldering - the thin trace will conduct less heat away from the pad.

Is that it or is there another reason for this very specific trace dimension recommendation?

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The short, thin traces act something like "thermals" in a plated-through-hole design. They minimize the effect of the heat from traces getting to the IC pads during soldering. That way, the IC temperature (which should be fairly even across the IC) will dictate when the solder melts (and solidifies).

MEMS accelerometers are more susceptible to package stress than other components. When the ICs are soldered to the board, asymmetries can be introduced. Rules such as "keep symmetric traces to assist with uniform package heating" become more important (even though they should always be considered!).

The PCBs get soldered in a reflow oven. In an ideal world, all the components would heat and cool together. What really happens is more complicated. Internal ground planes take longer to heat, because of their thermal mass and because they are insulated by the pcb itself. Vias connected to these planes act as heat sinks, cooling down traces. Wide traces and narrow traces heat unevenly, etc etc. Similar things happen when the board is cooling down.

In a small (0402, for example) component, if the solder on one pad melts before the solder on another pad, you can get tombstoning. Larger ICs (like yours) don't have this problem. But when the soldering stage is completed, and the board is cooling, some pads will invariably solidify before others. Since the IC is also cooling, therefore shrinking slightly, this can induce permanent mechanical stress on the part.

In the datasheet's "PCB Mounting Recommendations", Item 9:

Signal traces connected to pads should be as symmetric as possible. Put dummy traces on NC pads in order to have same length of exposed trace for all pads. Signal traces with 0.15 mm width and minimum 0.5 mm length for all PCB land pads near the package are recommended as shown in Figure 16 and Figure 17. Wider trace can be continued after the 0.5 mm zone.

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  • \$\begingroup\$ Does it means, it isolate the heat to the IC? \$\endgroup\$ – diverger Mar 30 '15 at 8:26
  • \$\begingroup\$ @diverger The boards get placed into a reflow oven. In an ideal world, all the components would heat and cool together. What really happens is complicated. Internal ground planes take longer to heat, because of their thermal mass and because they are insulated by the pcb itself. Vias connected to these planes act as heat sinks, cooling down traces. Wide traces and narrow traces heat unevenly, etc etc. The IC is warming up, too. I believe the intent of this guideline is to minimize the trace differentials from actually getting to the IC. \$\endgroup\$ – bitsmack Mar 30 '15 at 8:34
  • \$\begingroup\$ Oh, you mean that related to the heat when soldering, not working. These "neck downs" help the IC pins and the IC itself stay at same temperature, that say, a "thermal island", right? \$\endgroup\$ – diverger Mar 30 '15 at 8:45
  • \$\begingroup\$ @diverger Oh, I see! Yes, you're right, sorry that I wasn't clear. I've edited my answer a bit. Thanks :) \$\endgroup\$ – bitsmack Mar 30 '15 at 9:10
  • \$\begingroup\$ I've edited the answer to include @diverger 's clarifications. \$\endgroup\$ – bitsmack Mar 30 '15 at 18:09

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