I'm given a task to design a 4-bit register using D Flip-Flops (and MUXes) that operates according to the following selection inputs:
S1S0 = 00, No Change;
S1S0 = 01, Register is Cleared to 0;
S1S0 = 10, Current State is Complemented;
S1S0 = 11, Parallel Data is Loaded.
Below is what I've made, but I'm not so sure if I've implemented it correctly.
Could you correct me if there's anything that's incorrect or that I should improve?