I have a 4 to 1 mux that receives its data inputs and select inputs from edge clocked shift registers . Also the output of the mux goes to another shift register(call it the output register) as well. Should the clocking of all these register be synchronous or should I clock the data input and select registers on the leading edge of the clock and clock the output register on the falling edge of the clock? What's the ideal way of doing this?
Synchronous clocking works well. Prop delay of mux must be less than one clock cycle and output will be delayed one clock cycle from input.
There's rarely a single best way in doing things when it comes to circuits. There's always the best way given your design constraints. As the comment to your question says, using the same edge to sample the output and the input SRs is incorrect.
That leaves you with two options - either sample the output on the edge immediately following the sampling of the inputs (falling edge for the output, after the rising edge for the inputs) or sample the output one whole clock period after the inputs (rising edge for the inputs and the next rising edge for the outputs).
Now you can think about what advantages and disadvantages exist for these two cases.
This is the same as using multiple clocks (in or out of phase) in this case since you can achieve the same behavior by varying the time period and duty cycle of the single clock.