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For example, in the picture above, how do M5 and M6 really work? how can they be turned on by simply asserting WL? wouldn't the transistors turn on or off based on the gate-source voltage?

I don't understand how, for example, it would be possible to turn on M6 when there is a 1 stored in Q. In that case asserting WL would only bring the gate-source voltage to 0, how can that be enough to turn it on?

Since I'm not satisfied with the only answer, especially since it seems to contradict itself regarding the pre-charging, I'm expanding it a little bit:

The usual explanation of the operation of the SRAM cell relies on both access transistors being turned on. Here (page 17) you can find an example. So I don't understand how the access transistors could be both turned on if the source was on the side of the bit lines (because you are bringing BOTH bit lines to HIGH during a read operation), or even if the source was on the side of the inverters (because then only one access transistor would be turned on during a write operation, the same that would be turned on during a read operation (because now the only thing that matters to turn on the access transistors is Q and -Q: remember that source is on the side of the inverters)). If both reading and writing turned on the same transistors provided that the contents of the cell are the same, then what's the difference between reading and writing? I don't think it's just the sense amplifier. I would like for someone to clear these doubts.

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2 Answers 2

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When reading an SRAM bit, both column wires can be driven high (precharged) before raising the row wire high; one of them will then be pulled low, while the other one won't and will remain in the precharged state.

To write an SRAM bit, one of the column wires should be pulled low while the other is either precharged or pulled high. Turning on the access transistor won't do much on the side whose column is pulled high, but the access transistor on the other side will overpower the high-side PFET within the memory cell; doing that will in turn turn on the high-side PFET on the other side.

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  • \$\begingroup\$ When you say "one of them will then be pulled low, while the other one won't and will remain in the precharged state.", are you assuming that the source of the access transistors is connected to the inverters? because otherwise I don't see how it could be pulled low since the transistor wouldn't even turn on. Regarding the writing process, and considering that the source must be connected to the inverters, then how could you possibly turn on the transistor that is on the side of the cell that is storing a 1? what if that bitline is the one that holds the 0 that allows the cell to be written? \$\endgroup\$
    – 4nt
    Commented Apr 1, 2015 at 0:04
  • \$\begingroup\$ Here is a source that, as you said, says that "High bitlines must not overpower inverters during reads", "but low bitlines must write new value into cell". My problem is that I don't see how you can make sure that the low bitline access transistor is turned on, since as previously said, for the reading process to be possible you need the source terminals to be on the side of the inverters. \$\endgroup\$
    – 4nt
    Commented Apr 1, 2015 at 0:10
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    \$\begingroup\$ @Ant: The construction of a power MOSFET is completely different from that of the monolithic ones on an IC. In a power MOSFET, the substrate is the drain and the base is connected to the source; consequently, the source and drain are different. In a monolithic MOSFET, the base is the substrate, which is separate from both the source and the drain. While it's possible to construct a monolithic MOSFET asymmetrically so as to favor current flow in one direction or the other, in many cases the source and drain are identical. \$\endgroup\$
    – supercat
    Commented Apr 1, 2015 at 15:54
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    \$\begingroup\$ @Ant: A monolithic N-channel MOSFET will conduct whenever either the source or drain is at least ~0.7 volts more negative than the gate, and will conduct better (up to a limit) the higher the voltage. If the gate is at VDD and either end is at VSS, it will conduct well unless/until both ends are at VSS. \$\endgroup\$
    – supercat
    Commented Apr 1, 2015 at 16:59
  • \$\begingroup\$ That's what I wanted to know, thanks. Do you know where I could read more about the fundamentals of mosfets (or even bjts)? preferably a good book. Thanks again. \$\endgroup\$
    – 4nt
    Commented Apr 1, 2015 at 22:19
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The bit line is the source. To write a zero the bit line is driven low and M6 is turned on. M6 is designed to just sufficiently overdrive M4. Feedback of the latch completes the latching action. M5 operates in a like manner to write the one state.

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  • \$\begingroup\$ What about the pre-charge of the bit lines when reading? how would it work then? and what about writing a 1? \$\endgroup\$
    – 4nt
    Commented Mar 31, 2015 at 5:03
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    \$\begingroup\$ When the bit lines are pre-charged they are not driven and are not capable of flipping the latch. Charged is simply drained when the write line is turned on, by the side of latch that has the zero. Previous answer states how to write the "1" state. \$\endgroup\$
    – Martin McClurg
    Commented Mar 31, 2015 at 5:20
  • \$\begingroup\$ Thanks, so according to this you need both bit lines. I thought it was possible to make an SRAM cell with only one bit line. Also, I thought pre charging brought both bit lines to a logic 1, how can you then turn on the access transistors? I don't see how the side of the latch would matter in that case. \$\endgroup\$
    – 4nt
    Commented Mar 31, 2015 at 5:26

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