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How do I make sure that my rise and fall times are balanced between input and output in a CMOS design?

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  • \$\begingroup\$ Simulation of your design in whatever process node you're using. \$\endgroup\$ – horta Apr 1 '15 at 5:03
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Scale your pull-up PMOS circuitry to have the same conductance as the pull-down NMOS circuitry. For an inverter, this means scaling the PMOS to be 2-3× wider than the NMOS, because holes are 2-3× less mobile than electrons.

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