In a cmos driver what controls the amount of current it can source or sink? Is it the combined RDS on of the internal FETs? When you try to pull a line low I guess there's voltage stored in the capacitance of the trace and the current from that flows through the bottom FET and it's on resistance to gnd?
Second question how do they do slew rate control in a cmos I/O buffer is there a short burst of current from a one shot or something like that?
I have a clock coming out of an FPGA at 50Mhz, and for some reason it doesn't get to GND, maybe a few hundred mV above it. It does flatten out though. So I was thinking maybe it doesn't have enough pull to get it down to GND before the start of the next cycle. That made me wonder how a real CMOS I/O pad actually works.
I should add the trace is very long maybe about a foot, but impedance controlled to 50Ohm.