lets say we are given a sequential circuit ( e.g. a conventional D latch ) how should i go about detecting if it has a race condition or not ?
I would recommend googling about asynchronous circuit analysis.
What you should do is to first determine all the feedback loops in the circuit. i.e. Y = X'Z or with whatever assignment convention you're used to. Output as a function of all inputs.
Then create a state table like in the picture below. [The top row with the "Next State" header are the inputs]
You'll see a race condition when an input requires a Present State to go to a Next State that would require more than one bit change (fundamental mode).
A race occurs with more than one bit change in state transitions because two bits are "racing" to be the other. For example 00 -> 11. It can be 01 first, or 10 first, and this may cause problems. When this leads to problems, it's called a critical race. But if this race condition eventually leads to the final or intended state anyway, it's ok. For example, with an input of 1, 00->11 is expected. But with an input of 1, the state 10 leads to next state 11, and the same is with 01 leading to next state 11. So you have no problem.
An easier table to see this would be following the format of the following: The "Y2Y1" are the present states and the "W2W1" are the next states. Just encircle the states the next states that are the same as the present states. These are the stable states. If there's a column without a stable state, there's instability.
There's much more to do here. Anyway, another thing with your question, it's also nice to create a state diagram that follows a one bit change arrangement. And if there's any cross between states (where there's more than one bit change), depending on how you arranged it, then there's a race.