I've a stupid problem and I don' figure out how I can solve it. In my design I'm using a rising edge detector. The problem is that ActiveHDL doesn't simulate it in the way that I expect. The VHDL code is :
process (clk_i, rst_i) begin if ( rst_i = '1' ) then wb_IO_cyc_i_d <= '0'; wb_IO_cyc_i_edged <= '0'; elsif (rising_edge(clk_i) ) then wb_IO_cyc_i_d <= wb_IO_cyc_i; wb_IO_cyc_i_edged <= ( not wb_IO_cyc_i_d ) and wb_IO_cyc_i; end if; end process;
The problem is that the simulation is the following
The signal wb_IO_cyc_i_d should be delayed of 1 clock cycle but it doesn't. Someone can tell me why?