# Range of MIPS j instruction

I understand that for MIPS-32, the first 4 bits of the address to jump to are taken from the first 4 bits of the address of j instruction, which means that we have a boundary of 2^28 bits around the address of the j instruction that we can jump to. Online it says this boundary is 256MB but 2^28 bits is 32MB and not 256MB. Can anyone explain why it is 256MB?

Addressing in most CPU cores I know works on a per-byte basis. You don't address individual bits.

The MIPS requires it's instructions to be 4-byte (word) aligned - i.e. the two LSBs are always zero. That way, they're not encoded in the instructions.

@sherrelbc's answer explains it quite thoroughly, although I like the semantics of "word-aligned" more, than "word-addressed".

Direct addressing means specifying a complete 32 bit address in the instruction itself. However, since MIPS instructions are 32 bits, we can't do that. In theory, you only need 30 bits to specify the address of an instruction in memory. However, MIPS uses 6 bits for the opcode, so there's still not enough bits to do true direct addressing. Instead, we can do pseudo-direct addressing. This occurs in j instructions.

| Opcode  |              Target              |
|---------|----------------------------------|
|  B31-26 |               B25-0              |
| oooo oo | tt tttt tttt tttt tttt tttt tttt |


26 bits are used for the target. This is how the address for pseudo-direct addressing is computed.

PC <- PC31-28::IR25-0::00

Take the top 4 bits of the PC, concatenate that with the 26 bits that make up the target, and concatenate that with 00. This produces a 32 bit address. This is the new address of the PC.

So, 26 bits left shifted by two gives a relative address boundary of $2^{28}.$

$2^{28} bytes$ is $256 MiB$, or $256*1024^2$.

• The MIPS architecture addresses instructions by the word. Commented Apr 3, 2015 at 13:43
• @sherrellbc Yes, you're right, I'll fix the answer. Commented Apr 3, 2015 at 13:50

Actually, the first 6 bits of the instruction are the opcode. These bits are used by the control module in the datapath to determine what control signals to assert to facilitate execution of the instruction.

The opcode is conitained in bits 31 to 26, shown feeding into the Control module. As you can see from the picture above, the lower 26 bits from the instruction are shifted left twice and concatenated with the upper 4 bits already contained in the Program Counter (PC). This is a direct result of MIPS being word addressed (32 bits = 4 bytes = 1 MIPS word) rather than byte addressed, so the double left shift allows us to address 2^28, or 268,435,456 (256 MiB), instruction words within the range of the 4 most significant bits of the PC. If the opcode is such that a jump is to be executed then the top-right mux selects this new concatenated PC value and the next instruction to be fetched will be at the new address.

Actually, the PC is already incremented by 4, or one instruction, before being concatenated.

• I thought MIPS was byte-addressable? Although instructions are word-aligned. Commented Apr 3, 2015 at 13:46
• Also, I disagree with this: "the double left shift allows us to address 2^28, or 268,435,456 (256 MiB), instruction words offset from the current one." If our j instruction is at 0xFFFFFFFF, then whatever we jump to must have an address starting with "F". Clearly it isn't possible to jump 2^28 words after 0xFFFFFFFF under the above constraint. However we can jump to any address within the 256 MB space that contains all addresses starting with "F". Commented Apr 3, 2015 at 13:51
• @Vizuna, data memory is byte addressable; I was referring to the instruction memory addressing. And yes, you are correct in what you have said. Although, you still have a range of 256MiB instructions in either case. Also, pointing out that we cannot jump past 0xFFFFFFFF is obvious. The PC cannot address instruction memory beyond this point. In fact, such addresses do not exist in MIPS anyway. Commented Apr 3, 2015 at 14:24