# Asynchronous reset in verilog

I am new to verilog and having a bit of trouble getting along with it.

I read about asynchronous and synchronous reset and i think i got hold of it but while implementing the same with verilog i am not able to understand a line of code which i saw on this website.

In the asynchronous reset code why are we using the always @ (posedge clk or posedge reset) instead of using always @ (posedge clk ).

I mean how are the two lines of code able to differentiate which is asynchronous and which is synchronous?

always @ ( signal 1, signal 2......) is a construct used in behavioural modelling.

The code which is present in the block following this construct will run only when any of the signals in the sensitivity list viz signal 1, signal 2... changes.

If you put only posedge clock in the list, the code will run only when there is a positive clock edge and not otherwise. You can use this to create clocked circuits which respond to no other signals but clock. For synchronous reset, then you will write

always @ ( posedge clock)
begin
if (reset)  //Do something
else     //Do something else
end


For your case, you want asynchronous reset. Asynchronous reset means that your circuit should reset whenever reset signal is active 'Irrespective' of clock. Naturally, this should be included in the sensitivity list.

always @ (posedge clk, negedge reset_n)
begin
if ( 'reset_n) //Then reset (active low).
else  // Do something else
end

• For the always @(posedge clk, negedge reset_n) Xilinx synthesizer reports: Synth 8-91 ambiguous clock in event control Jan 31 '21 at 19:34

The latter example is typically implemented as follows

always @(posedge clk) begin
if(reset)
reg <= 0; //reset condition
else
reg <= whatever; //non-reset condition
end


The block is only executed at the rising edge of clk, which makes the reset below synchronous.

The asynchronous reset adds to the sensitivity list with a new signal -- reset. When you say:

always @(posedge clk or posedge reset) begin
if(reset == 1'b1)
reg <= 0; //reset condition
else
reg <= whatever; // non-reset condition
end


Now if reset rises independently of the clock you can enter the reset condition. This is an asynchronous reset. The key word is "or".

Briefly, if you put only clk in the sensitive list, and rst in the body part of always together with other assignment, you can find that reset operation only happen at the rising edge of clk just like other assignment, which means it is a synchronous reset.

However, if you put both clk and rst in the sensitive list, reset operation will happen whenever you input a negedge of rst. In this situation the reaction of rst no longer need to wait for next posedge of clk. Though reset and clock can still happen at the same time in this kind of design, but in most case, they are asynchronous.