I am new to verilog and having a bit of trouble getting along with it.
I read about asynchronous and synchronous reset and i think i got hold of it but while implementing the same with verilog i am not able to understand a line of code which i saw on this website.
In the asynchronous reset code why are we using the
always @ (posedge clk or posedge reset) instead of using
always @ (posedge clk ).
I mean how are the two lines of code able to differentiate which is asynchronous and which is synchronous?