Yes, it's a valid question, and you've just about got the whole answer already.
Let's call the PROMs U0 and U1. Assuming the decoder Enable selects U0 when A10=0 and U1 when A10=1.
The A0-A9 address bus drives both PROM address inputs. The decoder ensures that only one PROM is enabled, depending on the A10 address input. So D0-D8 will be driven by the U0 PROM when A10 is 0, and D0-D8 will be driven by the U1 PROM when A10 is 1.
Since the decoder never enables both U1 and U2 at the same time, it's legal to connect the U0 D0-D8 outputs and the U1 D0-D8 outputs to the same data bus. (This would not be OK if both outputs could be enabled to drive at the same time, because each signal can only have one source.)
This is very commonly done in FPGA where there are small block memory units available, that can be stitched together into larger memory banks as needed.