I have to interface a video format converter with a ADC IC, which converters RGB analog data to digital. The connection between this ADC and Converter is a 20 bit data bus which clocks at about 170MHz. Since I have the PCB area constraints I cannot perfectly match the trace length of this data bus. I heard that there are matched trace length tolerances depending on frequency so that it will not damage the signal acquisition by the destination.

My question is how to calculate trace length tolerances in a High Speed PCB design? (in differential pair routing and high speed data bus routing)

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    \$\begingroup\$ Usually there are layout guidelines published by the various chip vendors. If not, there might be setup and hold-time listed. You mention differential pairs. Is the 20-bit data bus differential? \$\endgroup\$ – mkeith Apr 4 '15 at 4:12
  • \$\begingroup\$ No its not a differential data bus. Data sheet only mentioned about the bus speed, to keep trace shorter and lengths to be matched. \$\endgroup\$ – Thilina S. Ambagahawaththa Apr 4 '15 at 5:32

Length matching is about timing so if you want to know how tightly you have to length match you have to understand the timing budget for your interface. Signals will leave your source, and arrive at your destination with some timing relationship. Your receiver requires a certain timing relationship between clock and data in order to be guaranteed to function correctly. This is usually defined as setup and hold time, or how long before the clock edge your data needs to be valid, and how long after it must stay valid.

There are several things in a system which eat into this budget, one of which will be your routing. Sometimes a manufacturer will tell you this information, other times you must derive it from the input and output timing data of your transmitter and receiver. Of course it's easy to just say well I must match exactly, because then you don't have to think about it :)

But let's think about it for a minute. You have a 170Mhz signal? That's a period of 5.882ns. What would happen if you routed all your data to within one inch of clock. What would be the worst case timing difference. Propagation time for a top layer trace, a microstrip is about 150ps/in. So a 1 inch difference will skew a data signal from clock +/- 150ps. That's really not bad at all considering your 5.882ns clock period. In fact 170Mhz is really not that fast.

If you understood the output skew from your transmitter, and your setup and hold times for your receiver you could come up with a number for the acceptable routing delay. Of course there are other factors, clock jitter, ISI, etc, but this should give you a good idea of what you can do.

  • \$\begingroup\$ Very concise, I like the answer. I am curious, however (please bear with me), is capacitance on the line going to further worsen performance as distance is added, or is this its own issue more or less unrelated. \$\endgroup\$ – mcmiln Apr 4 '15 at 7:56
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    \$\begingroup\$ The capacitance is already accounted for in the propagation delay. Not to get too deep but propagation delay per unit length (say 1 inch) is sqrt(Lo * Co), where Lo is the inductance per unit length and Co is the capacitance per unit length (again think capacitance and inductance per inch for instance. When you add more trace you're not just adding capacitance. Now there are other effects that could affect your rise time such as the input capacitance of your receiver, connectors or vias. Then there are losses for other reasons at high speed but probably not something you need \$\endgroup\$ – Some Hardware Guy Apr 5 '15 at 4:00
  • \$\begingroup\$ to worry about at 170MHz. \$\endgroup\$ – Some Hardware Guy Apr 5 '15 at 4:00
  • \$\begingroup\$ Great, thank you. Plenty to play around with there. \$\endgroup\$ – mcmiln Apr 5 '15 at 11:07

In the absence of a specification for the bus standard or the receiver timing, you can apply a rule of thumb such as keeping the skew to less than 5% of the clock period. Signals on an FR4 PCB travel at approx half the speed of light, so you'd want to make your longest trace no more than 44 mm longer than the shortest trace. Not too tricky. Preferably, the length of the clock trace should be somewhere in between.

Incidentally, analog signal integrity may be a bigger problem than digital in this design. You'll want to take care not to couple switching noise from the digital lines into the analog input signals. Read Henry Ott's tips (particularly #4, 8, 9, 10, 17) and preferably buy his book.


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