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In Verilog, I am trying to store the input up to 4 previous values and then operate on them.The code is fine in simulation but on FPGA, it calculates output with the current input instead of previous ones. what are the registers not being synthesized to memory blocks where past input can be stored? the past input values are supposed to change only on change in the current input.
All the operations have to be performed with stored 4 values of x-> x0,x1,x2,x3 Works in simulation, fails in hardware (Spartan 3E) Top module:

module main(input [7:0] x,input clk,reset, output [15:0] y,output reg[7:0] x0,x1,x2,x3
);  
  //reg [7:0]pxe[0:3];  
  reg [7:0] h0,h1,h2,h3;   
  reg [7:0] addr;  
  wire [7:0]m0,m3,m1,m2;   
  wire [3:0]s2,s3,s1,s0;  
  wire [15:0] mult0,mult1,mult2,mult3,out0;  
  wire [15:0] sout0,sout1,sout2,sout3;  
  wire [7:0] xconv0,xconv1,xconv2,xconv3;  
  wire [7:0] sin0,sin1,sin2,sin3;  
  wire [15:0] po0,po1,po2,po3;  
  //reg [3:0] s0;  
  assign out0=8'd0;  

  check inst_1(h0,clk,reset,m0,s0);  
  check inst_2(h1,clk,reset,m1,s1);  
  check inst_3(h2,clk,reset,m2,s2);  
  check inst_4(h3,clk,reset,m3,s3);  

  cla3input int_1(mult0,sout0,out0,po0);  
  cla3input int_2(mult1,sout1,po0,po1);  
  cla3input int_3(mult2,sout2,po1,po2);  
  cla3input int_4(mult3,sout3,po2,po3);  

  xconv ist_1(x0,s0,xconv0);  
  xconv ist_2(x1,s1,xconv1);  
  xconv ist_3(x2,s2,xconv2);  
  xconv ist_4(x3,s3,xconv3);  

  shiftin it_1(h0,xconv0,sin0);  
  shiftin it_2(h1,xconv1,sin1);   
  shiftin it_3(h2,xconv2,sin2);  
  shiftin it_4(h3,xconv3,sin3);  

  shifter i_1(sin0,s0,sout0);   
  shifter i_2(sin1,s1,sout1);  
  shifter i_3(sin2,s2,sout2);  
  shifter i_4(sin3,s3,sout3);  

  booth_a is_1(mult0,x0,m0,h0);  
  booth_a is_2(mult1,x1,m1,h1);  
  booth_a is_3(mult2,x2,m2,h2);  
  booth_a is_4(mult3,x3,m3,h3);  

  assign y= po3;   
    always@(posedge clk)  
    begin  
      h0<=5;  
      h1<=-3;  
      h2<=1;   
      h3<=2;  
      if (reset)  
      begin  
        x0<=0;  
        x1<=0;  
        x2<=0;  
        x3<=0;   
      end  
      else  
      begin  
        x0<=x;  
        x1<=x0;  
        x2<=x1;  
        x3<=x2;  
      end  
    end  
endmodule     
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1 Answer 1

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What you are synthesizing are not memory blocks but rather register with synchronous reset - which should act exactly as you described so that is not the problem you are seeing. So it is not completely clear to me where the problem is. I suggest you add some details (e.g. version of the tools you are using to synthesize this, what other registers are in the design, embedded in blocks), then it shoudl be easier to help you. You can also check the warnings and the netlist pre- and post-synthesis to check if the registers were implemented.

PS: are you aware that h0,h1,h2,h3 are fixed to constant values - is that what you want to do? If so, you can move them out of the register block.

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